imx7 GPIO Behavior description

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imx7 GPIO Behavior description

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ahonkan
Contributor I

I'm trying to understand from the imx7 Reference Manual and the Datasheet, how to go about configuring the GPIO for following operations:

- Push Pull

- Drive Low, Pull-Up High

- Drive High, Pull-Down Low

Using IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK and  as reference, please describe the appropriate register settings to get the above GPIO behavior?  The documentation is pretty sparse in describing the GPIO internal structure and how output stage can be configured. 

AN5078 does a good job of showing a simplified internal structure (fig 6) but that doc doesn't apply to imx7 SOC. 

 

Thanks

 

 

 

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ahonkan
Contributor I

Apologies, I think I misread your response.

- Push-Pull is enabled when the GDIR is 1, output.  Then writing to DR will change state on the output line.

- For driving 0, i set GDIR to 1 and DR to 0..  When I want to release the line, I set the PAD PS & PE and then set the GDIR to 0 for the line to be pulled high.

Let me know if this is the correct method.  Thanks again!

 

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igorpadykov
NXP TechSupport
NXP TechSupport

>When I want to release the line, I set the PAD PS & PE and then set the GDIR to 0

for the line to be pulled high. Let me know if this is the correct method.

 

yes this is correct.

 

Best regards
igor

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ahonkan
Contributor I

Thanks  Igor.  So to confirm,

- if I set the GPIO GDIR as output, the PAD_* settings PS and PE are ignored, and the output is Push-Pull

- If I set GPIO_GDIR as input, the PAD_* settings PS and PE take effect

For the Drive Low, Pull-Up High, I don't understand how I'm able to Drive Low if I configure the DIR to be input.  Shouldn't the GPIO output block be disabled/tri-stated and only enable  the input?  It seems like there is a potential for contention if I set the DIR as input and set DR to be 0.

This behavior you've described is not documented, or maybe I'm not understanding the documentation correctly:

8.3.5.1 GPIO data register (GPIOx_DR) :  If GDIR[n] is cleared and IOMUXC input mode is GPIO, then reading DR[n] returns the corresponding input signal's value.

There is no mention of what happens on the Pad if you set  or clear the DR when GDIR[n] is cleared (input). 

 

Thanks

 

 

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igorpadykov
NXP TechSupport
NXP TechSupport

 

Hi Avinash

 

>There is no mention of what happens on the Pad if you set or clear the

>DR when GDIR[n] is cleared (input).

 

Pad settngs do not depend on GDIR[n].

 

> if I set the GPIO GDIR as output, the PAD_* settings PS and PE are ignored,

>and the output is Push-Pull

 

they are not ignored. With setting PE=0 Pull Disabled, "output is Push-Pull".

 

>For the Drive Low, Pull-Up High, I don't understand how I'm able to

>Drive Low if I configure the DIR to be input.

 

what do you mean by "Drive Low if I configure the DIR to be input" ?

 

 

Best regards
igor

 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Avinash

 

>Push Pull

1. set IOMUXC_SW_MUX_CTL* register MUX_MODE to GPIO,

sect.8.2.7.129 SW_MUX_CTL_PAD_SAI1_RX_BCLK SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK)

i.MX 7Dual Applications Processor Reference Manual

2. set that GPIO registers GPIOx_GDIR as output, write data to GPIOx_DR,

sect.8.3.5.2 GPIO direction register (GPIOx_GDIR),

sect.8.3.5.1 GPIO data register (GPIOx_DR)

 

>Drive Low, Pull-Up High

 

for "Drive Low" follow above description and write "0" to GPIO data register GPIOx_DR.

for "Pull-Up High" set GPIO direction register GPIOx_GDIR as input,

set SW_PAD_CTL_PAD* register with appropriate pull settings "PS", "PE" :

sect.8.2.7.285 SW_PAD_CTL_PAD_SAI1_RX_BCLK SW PAD Control
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK)

 

Best regards
igor

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