IMX8M Mini SPI M4 and A core communication issue

[Dhevan]

Hi,

      ECSPI1 used configured in linux device tree file.

      ECSPI2 used configured in M4 core.

      M4 core ecspi2 running fine data transferred to linux via rpmsg_lite_tty ipc mechanism.

      If we run linux ecspi1 and m4 ecspi1 on parallel in linux ecspi1 side data loss is there.

      If we run only linux ecspi1 there is no data loss.

      Previous we used to read two spi in linux user space at time we have face data loss issue that's why we are planned to use M4 core for one more spi same issue is coming.

      1) ecspi1 used sdma1 interface m4 core imx8mm-evk-rpmsg.dts file sdma disable line removed really sdma1 has to disable ?

      2) M4 ecspi2 run and ecspi1 runs in linux space both the core are running independent then how affecting linux and m4 spi solw down the operation and data loss.

      3) m4 core not use i2c2 and linux dts file configured i2c but in linux /dev/i2c does not present m4 core using i2c2 interface internally ?

      Our ultimate goal we has to use two spi interface should run independent then only we can read 13K data per second.

Thanks & Regards,

          Vasu

[Dhevan]

M4 sdk fsl_ecspi.c file dma used

void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz)

{

    assert((config != NULL) && (srcClock_Hz != 0U));

#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)

    /* Open clock gate for SPI and open interrupt */

    CLOCK_EnableClock(s_ecspiClock[ECSPI_GetInstance(base)]);

#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

    /* Reset control register to default value */

    ECSPI_SoftwareReset(base);

    /* Config CONREG register */

    base->CONREG =

        ECSPI_CONREG_BURST_LENGTH((uint32_t)config->burstLength - 1UL) | ECSPI_CONREG_SMC(1U) | ECSPI_CONREG_EN(1U);

    /* Config CONFIGREG register */

    ECSPI_SetChannelConfig(base, config->channel, &config->channelConfig);

    /* Config DMAREG register */

    base->DMAREG |=

        ECSPI_DMAREG_TX_THRESHOLD(config->txFifoThreshold) | ECSPI_DMAREG_RX_THRESHOLD(config->rxFifoThreshold);

    /* Config PERIODREG register */

    base->PERIODREG |= ECSPI_PERIODREG_CSRC(config->samplePeriodClock) |

                       ECSPI_PERIODREG_SAMPLE_PERIOD(config->samplePeriod) |

                       ECSPI_PERIODREG_CSD_CTL(config->chipSelectDelay);

    /* Config TESTING register if enable the loopback function. */

    base->TESTREG |= ECSPI_TESTREG_LBC(config->enableLoopback);

    /* Set baud rate */

    ECSPI_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);

}

    Due to this dma affecting linux core spi ?