imx6quad device tree SS with ECSPI or with GPIO?

[J_W]

Hi,

I am attempting to activate the ECSPI on my imx6q and I am a bit confused about discrepancies between the Reference Manual and my provided device tree - particularly regarding setting up the slave select pin. It turns out that the device tree has set up the SS with a GPIO instead of the ECSPI_SS mux command, is there any particular reason for that?

The default device tree:

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	fsl,spi-num-chipselects = <2>;
	cs-gpios = <
		&gpio2 30 GPIO_ACTIVE_HIGH
		&gpio3 19 GPIO_ACTIVE_HIGH
	>;
	status = "okay";

	spidev0: spi@0 {
		compatible = "spidev";
		reg = <0>;
		spi-max-frequency = <54000000>;
	};

	spidev1: spi@1 {
		compatible = "spidev";
		reg = <1>;
		spi-max-frequency = <54000000>;
	};
};

pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x0b0b0
			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x0b0b0
			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x0b0b0
			MX6QDL_PAD_GPIO_19__ECSPI1_RDY		0x0b0b0
			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x0b0b0 /* SPI CS0 */
			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x0b0b0 /* SPI CS1 */
		>;
	};

Note that the SPI CS is set up as MX6QDL_PAD_EIM_EB2__GPIO2_IO30.

However, in the reference manual there is another option, namely MX6QDL_PAD_EIM_EB2__ECSPI1_SS0. Why is this not used in the default device tree? (imx6q-tx6q-1036.dtsi)

I would like to use the built in SS functionality of the ECSPI instead of doing it manually. I'm uncertain on how to edit the device tree, in particular the cs-gpios part, is that part even required if the pin is set up as ECSPI1_SS0?

I was thinking about changing it to

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	fsl,spi-num-chipselects = <1>;
	status = "okay";

	spidev0: spi@0 {
		compatible = "spidev";
		reg = <0>;
		spi-max-frequency = <10000000>;
	};
};

    pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x0b0b0
			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x0b0b0
			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x0b0b0
			MX6QDL_PAD_GPIO_19__ECSPI1_RDY		0x0b0b0
			MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 		0x0b0b0
		>;
	};

Or do I need to describe the SS pin somehow inside the ecspi1 block?

[AldoG · Accepted solution]

Hello,

Before kernel 4.14, native chip select usage on spi-imx driver was not functional so GPIO implementation was used, from 4.14 kernel and later this has been fixed so it is safe to use native CS.

Best regards,
Aldo.