imx6ULL RTS signal

[roshandsouza]

Hi All,

We are using the imx6ULL processor MCIMX6Y2CVM05AA and RS485 transceiver IC ST485BDR in our design.We are facing a similar issue related to RS485 RTS signal as above.We are using the UART port 2 of the processor ( UART2_TX transmit function,UART2_RX for receive function,UART3_RXD pin for TX enable and RX enable of RS485 transceiver).We are using kernel version 4.1.x.x.

We were able to toggle the RTS line of UART2 by configuring it as a GPIO line but we are missing few bytes and not able to receive the complete data.

The transit enable from ULL processor is not going low immediately after the transmission is completed( Highlighted in green in attachment). We are losing few bytes as the delay between the Rx enable and Rx data is very small (Highlighted in Red in attachment).

How to make the RTS signal low immediately after the transmission is over ?

[weidong_sun]

Hello Roshan,

    In DCE mode, UART_CTS is used to control data IO directions, you multiplexed RTS to be   GPIO and used it to control TX/RX , exactly, which will cause data to be lost. Because you don't know when TX / RX is done. RS485 is half-duplex communication.

    For RS485 design, I have 3 suggestions for you :

1. Using UART CTS to control IO direction of data.

This is supported by UART IP, you can find the function in i.MX6UL Reference manula.

2. Using Hardware control it, don't need any code in software.

3. Using GPIO to control DE/RE#

Since you used GPIO to do it, I think you should check the "empty interrupt" of UART TX FIFO , if the interrupt occurs, GPIO should be switched to RECEIVE (maybe pull it down to LOW)

Have a nice day!

NXP TIC weidong sun