imx6 secure monitor code

[johnballance]

Hi

I hope I'm not missing the point, but...

to enable or disable the pl310 L2 cache controller I encounter an instruction 0xE1600070, which I suspect is the opcode SMC #0.  This I presume should invoke a small amount of code running in a secure monitor. Where can I find examples of this monitor, and also how do I load/initialise it please.

[Yuri]

Please look at  ARM TZ example, linked below.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15417.html

[johnballance]

Hi Yuri. Yes I'd found that. The issue I see seems to be that when I get control of the machine, after the IVT and DCD stuff has been run, it is on non secure mode.. i.e. secure configuration register data bit 0 = 0. The only way to get to secure mode from there is SMC #0, which appears to go to uninitialised code..  Can I setup, e.g. the secure vector base address register in the DCD code? if so how do I get there please

[matthewsealey]

Hi John,

It seems you have your bits backwards - the bottom bit of the SCR register is actually .NS which dictates that the world you "came from" (in the Secure Monitor) or want to transition to is Non-Secure - if set. That is to say, SCR.NS==0 is Secure and SCR.NS==1 is Non-Secure.

Here's the thing, though: if you can even read the value of the SCR, you are also in Secure world, because it is appropriately not readable in the Non-Secure world. It will cause an undefined instruction exception just from reading the SCR, because Normal (Non-secure) World software is not meant to know whether security extensions are even present let alone which world they are in - the effect of trying to read the SCR in Normal (NS) or no-Security-Extensions-present environments is identical in that regard.

The way SMC works is really simple - it causes an SMC exception at the secure monitor. There's no way to set either the secure monitor vector base address in IVT or DCD for i.MX processors, but it would be incredibly unfortunate if you - without loading any plugins or other code via the Boot ROM APIs - somehow dropped to Non-secure since then you'd lose all access to the L2 cache configuration and so on. Note that the ARM TrustZone API example is old and deprecated and generally people are pointed to this vendor who have an open-source implementation:

     Open Virtualization - ARM TrustZone and ARM Hypervisor Open Source Software

The real question here is how and where are you encountering this instruction, and if there is no secure environment for the SMC to enter, why is it even being executed if you are already in Secure world? Are you attempting to directly load software that was intended to run under a secure environment?

Ta,

Matt

[johnballance]

Hi Matt

Reply really appreciated.

I have now got on top of it.. there appear to be one or 2 'little

bits'that really need the secure code, so I needed to ensure a monitor

was installed. .. (in particular, access to L2 cache controller.)

For what it is worth, I now have a HAL up and running for RISCOS, though

it isn't in the public domain as yet.

Many thanks

John

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[matthewsealey]

Understood, I realise my reply was late (compared to when you asked the question!) but I really felt that the information isn't really well expanded on in the real world without digging through the ARM ARM (and the old TrustZone API example referenced really isn't the place ARM support points you at anymore).

It is REALLY interesting that RISCOS HAL - from your description - uses TrustZone functionality for the HAL calls...

[johnballance]

mmm

there are just a couple of calls to do with L2 cache that I found I

needed to do in the secure realm. The rest of the time is spent in

normal modes...

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