imx6 LPDDR2 parameter clarification

[tomcoggio]

reg 021b_0018 /021b_4018

WALAT

-

0

00000000

WALAT: Write Additional latency. Recommend to clear these bits. Proper board design should ensure that the DRAM devices are placed close enough to the MMDC to ensure the shew between CLK and DQS is less than 1 cycle.

I have the clock 65mm (~434pS) from the processor and the DQS lines are 81mm from the processor ( ~540pS) to the memory chip.

The memory is Micron  MT42L256M64D4LM-25WT  (400MHz LPDDR2)

Can someone tell me what the statement above " MMDC to ensure the shew between CLK and DQS is less than 1 cycle. " is referring to, because if both distances are less than 1cycle (2500pS) and yet the system wont run at 400MHz, it is ok at 380 MHz.

By setting the WLAT to 1, the system passes the memory test at 400 with flying colours.

My deduction from this is that the statement is referring to the return flight path ??? Could someone please explain if possible.

Thanks!

PS: prior to the WLAT of 1, the memory test would not pass at 1GHz processor speed. now it works with 1GHz also.

[Yuri · Accepted solution]

Hello,

   Generally RALAT / WALAT are used to compensate internal delays in order to provide

proper timings for internal output buffer enable signals, controlling internal FIFOs.

Really optimal values for RALAT / WALAT are board dependent and should be found

experimentally. Also, please refer to MMDCx_MDMIC[WALAT] description in the i.MX6

Reference Manual for more details, in particular, regarding to an issue, when the DQS signal

(delayed internally from SDCLK) may be cropped. To avoid it WALAT should be set 1.

  Please check if for Your board :

- Address and control signals  shorter than the clocks ;

- Longest clock trace must be <= 3 inches.

Have a great day,
Yuri

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