HI!
When i use fbset to set pixclock value 21000 picosecond and it fails: real clock does not exceed 24 MHz. That is because bit 1 of HW_CLKCTRL_CLKSEQ register is set to 0 so ref_xtal is selected to clock lcdif. I need to select ref_pix and enable PIX fractional divider in HW_CLKCTRL_FRAC with setting it`s value. I think its possible to do this by modify .dts file because driver code file drivers/clk/mxs/clk-imx23.c contains string
clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
So can anybody show me way how to do this or advice something else?
Thanks,
Anatol
已解决! 转到解答。
Please do not change dts. I create a patch for the clock driver, which should do the trick. But i can't test it.
Hi Stefan,
Unfortunately i do not understand well how linux clock framework works and how it communicates with dts blob. I saw in the clk-imx23.c implemented something about multiplexing clock which used to clock lcdif. I thought as its possible to select clock in dts file, so its possible to set mux parametrs.
Am i wrong? Do you know what is "lcdif_sel" in the clocks list?
I understand about the gist. I dont understand how to select ref_pix as clock source. I tried to set "clocks = <&clks 4>;" to bind lcdif with ref_pix. But then i got CLK_PIX gated off by bit 31 (CLKGATE == 1) of register HW_CLKCTRL_PIX.
May be i should to use lcdif_sel somehow?
Stefan, thank you!
Your method works fine.
Also exist alternative method suggested by Marek Vasut at [PATCH] clk: mxs: source LCD clock from PLL instead of from ref_xtal.
Yes, that was the case:
[PATCH] clk: mxs: source LCD clock from PLL instead of from ref_xtal
Stefan, do you plan to resend it?
Regards,
Fabio Estevam
Currently i don't have a test environment for i.MX23 or i.MX28.
Do you know any drawbacks of the this patch (higher power consumption etc)?
Is this patch compatible with i.MX280 since it has no lcdif interface?