iMx6Q uSDHC Multiple Block Read Problem

[cagatayozdemir]

Hi all,

I have a custom board based on Sabre Lite and I am adapting original QNX BSP provided for that board.

IPL bootrom is loaded from NorFlash over SPI. QNX IFS image is located in a uSD Card which is connected to SD3 channel. IPL code connects to SD Card, finds qnx-ifs and calculates block size with many single block reads (CMD17) without a problem. However, while trying to read the image with multiple block read (CMD18), inspite of getting response for the command transfer is not completed. To be more exact, uSDHC3_INT_STATUS (0x02198030) register's TC (#1) bit resides being 0 forever (Transfer is not completed).

SD Card has a FAT32 partition and works with Sabre Lite board. The BSP originally works for Sabre Lite board; I only changed some simple pin multiplexing and added debug codes. What may cause this problem?

[cagatayozdemir]

Thanks for the help Yuri!

Although our chip is 1.3 version and there is not heavy load since being in boot process, the problem seems to be related with internal DMA. For example, if simple internal DMA is used Multiple block read cannot be realized; additionally if ADMA1-2 is chosen then even Single block read cannot be done. In these situations, the Present State register shows me that SDOFF is set, in other words SD Clock is gated off.

I tried to re-assign SDCLKFS  and DVS fields of System Control register however couldn't restart the clock. What is the procedure to do this?

Also I tried to use external DMA for the transfer from internal buffer to the system. I disabled internal DMA and enabled external DMA from Vendor Specific Register. But internal buffer is again over and transfer cannot be finished succesfully again.

[Yuri · Accepted solution]

Hello,

1.

  The following feature sometimes took place if for old i.MX devices : (under heavy system load) the DMA
cannot serve the SDHC within the period of 16 SDHC clocks, the SDHC state-machine turns of the SDHC
clocks to avoid data overflow, since the state-machine is not designed to resume the clock when DMA access

is done after the mentioned period of time.

Workaround : check time-out status and rerun the clocks if complete flag is not observed in time.

2.

    Perhaps ERR004536 from the Errata takes place. Please refer to the Errata for more details.

http://cache.nxp.com/files/32bit/doc/errata/IMX6DQCE.pdf?fpsp=1&WT_TYPE=Errata&WT_VENDOR=FREESCALE&W...

Have a great day,
Yuri

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[cagatayozdemir]

Hi all again,

Boot code was changed according to Freescale DDR Testing tool and also it has passed over-night test successfully. Thinking that the driver code works for Sabre Lite board originally, is it possible to have a Signal Integration problem in the board for 25 MHz speed?

Cagatay