iMXRT1176 octal flash not working

[joogoosa]

Hello, we are making a custom board based on iMXRT1170 EVK 32171_C but use a different SDRAM and octal RAM, also differenced in power management.

We're trying to boot the device debug and erase (GUI tool), all three unsuccessful.

We have interesting observations from logic analyzer that the inverted Flash clock signal is not doing anything and data lines send single pulse in erase, debug and boot atemps. Only the SS0 and positive clock seem to work. (images attached).

Perhaps there's a harware issue?

FLASH USED: MACRONIX MX25UM51345G

BOOT SETTINGS:
BOOT_CFG[10]=1
BOOT_CFG[9]=0
BOOT_CFG[8]=0
BOOT_CFG[7]=0
BOOT_CFG[6]=0
BOOT_CFG[5]=0
BOOT_CFG[4]=0
BOOT_CFG[3]=0
BOOT_CFG[2]=0
BOOT_CFG[1]=1
BOOT_CFG[0]=1
BOOT_MODE[1]=1
BOOT_MODE[0]=0

MCUXpresso flashloader_cm7 example made to run from RAM:
deadbeee: Failed to execute MI command:
-data-disassemble -s 3735928558 -e 3735928610 -- 3
Error message from debugger back end:
Cannot access memory at address 0xdeadbeee

GUI flash tool from MCUXpresso command line while trying to erase flash:
Executing flash operation 'Erase' (Erase flash) - Mon Feb 07 15:55:30 EET 2022
Checking MCU info...
Scanning for targets...
Executing flash action...
SEGGER J-Link Commander V7.60b (Compiled Dec 22 2021 12:56:02)
DLL version V7.60b, compiled Dec 22 2021 12:54:46
J-Link Command File read successfully.
Processing script file...
J-Link>ExitOnError 1
J-Link Commander will now exit on Error
J-Link>r
J-Link connection not established yet but required for command.
Connecting to J-Link via USB...O.K.
Firmware: J-Link Lite-Cortex-M V8 compiled Sep 15 2016 12:05:01
Hardware version: V8.00
S/N: 518109715
License(s): GDB
VTref=3.313V
Target connection not established yet but required for command.
Device "MIMXRT1176XXXA_M7" selected.
Connecting to target via SWD
Found SW-DP with ID 0x6BA02477
DPv0 detected
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[3]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x84770001)
AP[1]: AHB-AP (IDR: 0x24770011)
AP[2]: APB-AP (IDR: 0x54770002)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p2, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
[0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
[1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
[2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[2][1]: E0001000 CID B105E00D PID 000BB002 DWT
[2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[2][3]: E0000000 CID B105E00D PID 000BB001 ITM
[1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[1][2]: E0042000 CID B105900D PID 004BB906 CTI
[0][1]: E0043000 CID B105900D PID 001BB908 CSTF
Cache: Separate I- and D-cache.
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Cortex-M7 identified.
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: SYSRESETREQ has confused core.
Found SW-DP with ID 0x6BA02477
DPv0 detected
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF01FE018
CPUID register: 0xF01FE019. Implementer code: 0xF0 (???)
Unknown core, assuming Cortex-M0
Found Cortex-M0 r1p9, Big endian.
Reset: Using fallback: VECTRESET.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
Reset: VECTRESET has confused core.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x6BA02477
DPv0 detected
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. No ROM table (AHB-AP ROM base: 0x00000000)
CPU could not be halted
Reset: Core is locked-up, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x6BA02477
DPv0 detected
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. No ROM table (AHB-AP ROM base: 0x00000000)
CPU could not be halted
Reset: Failed. Toggling reset pin and trying reset strategy again.
Found SW-DP with ID 0x6BA02477
SWD speed too high. Reduced from 2000 kHz to 1350 kHz for stability
DPv0 detected
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. No ROM table (AHB-AP ROM base: 0x00000000)
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: SYSRESETREQ has confused core.
Found SW-DP with ID 0x6BA02477
DPv0 detected
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. No ROM table (AHB-AP ROM base: 0x00000000)
Reset: Using fallback: VECTRESET.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
Reset: VECTRESET has confused core.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x6BA02477
DPv0 detected
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. No ROM table (AHB-AP ROM base: 0x00000000)
CPU could not be halted
Reset: Core is locked-up, trying to disable WDT.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x6BA02477
DPv0 detected
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. No ROM table (AHB-AP ROM base: 0x00000000)
CPU could not be halted
AfterResetTarget() start
AfterResetTarget() end
CPU could not be halted
****** Error: Could not find core in Coresight setup
Failed to halt CPU.
J-Link>exec EnableEraseAllFlashBanks
J-Link>erase
Without any given address range, Erase Chip will be executed
Erasing device...
CPU could not be halted
****** Error: Cannot read register 16 (XPSR) while CPU is running
Cannot read register 20 (CFBP) while CPU is running
Cannot read register 0 (R0) while CPU is running
Cannot read register 1 (R1) while CPU is running
Cannot read register 2 (R2) while CPU is running
Cannot read register 3 (R3) while CPU is running
Cannot read register 4 (R4) while CPU is running
Cannot read register 5 (R5) while CPU is running
Cannot read register 6 (R6) while CPU is running
Cannot read register 7 (R7) while CPU is running
Cannot read register 8 (R8) while CPU is running
Cannot read register 9 (R9) while CPU is running
Cannot read register 10 (R10) while CPU is running
Cannot read register 11 (R11) while CPU is running
Cannot read register 12 (R12) while CPU is running
Cannot read register 14 (R14) while CPU is running
Cannot read register 15 (R15) while CPU is running
Cannot read register 17 (MSP) while CPU is running
Cannot read register 18 (PSP) while CPU is running
****** Error: Failed to prepare for programming.
Could not preserve target memory.
Error while determining flash info (Bank @ 0x30000000)
ERROR: Erase returned with error code -1.
Script processing completed.
Unable to perform operation!
Command failed with exit code 1

MCU Boot Utility GUI Device status when connecting to device thru USB:

--------MCU device Register----------
HAB status = Open
--------MCU Flashloader info-------
Current Version = K3.0.0
Target Version = T1.0.4
--------MCU device eFusemap--------
BT_FUSE_SEL = 1'b0
When BMOD[1:0] = 2'b00 (Boot From Fuses), It means there is no application in boot device, MCU will enter serial downloader mode directly
When BMOD[1:0] = 2'b10 (Internal Boot), It means MCU will boot application according to both BOOT_CFGx pins and Fuse BOOT_CFGx
----------FlexRAM memory-----------
IOMUXC_GPR->GPR16 = --------
--------FlexSPI NOR memory--------
Page Size = 256 Bytes
Sector Size = 4.0 KB
Block Size = 64.0 KB

MCU Boot Utility terminal info:
Executing: \blhost -t 50000 -u 0x1FC9,0x013D -j -- get-property 1 0

toolStatus: 0
commandOutput: {
"command" : "get-property",
"response" : [ 1258487809 ],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 50000 -u 0x1FC9,0x013D -j -- get-property 17 0
toolStatus: 0
commandOutput: {
"command" : "get-property",
"response" : [ 0 ],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 5242000 -u 0x1FC9,0x013D -j -- load-image \ivt_flashloader.bin
toolStatus: 0
commandOutput: {
"command" : "load-image",
"response" : [],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 50000 -u 0x15A2,0x0073 -j -- get-property 1 0
toolStatus: 0
commandOutput: {
"command" : "get-property",
"response" : [ 1258487808 ],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 50000 -u 0x15A2,0x0073 -j -- get-property 1 0
toolStatus: 0
commandOutput: {
"command" : "get-property",
"response" : [ 1258487808 ],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 50000 -u 0x15A2,0x0073 -j -- get-property 24 0
toolStatus: 0
commandOutput: {
"command" : "get-property",
"response" : [ 1409351684 ],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 50000 -u 0x15A2,0x0073 -j -- efuse-read-once 22
toolStatus: 0
commandOutput: {
"command" : "efuse-read-once",
"response" : [ 4, 8 ],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 5242000 -u 0x15A2,0x0073 -j -- read-memory 1074675776 4 \vectors\readReg.dat 0
toolStatus: 0
commandOutput: {
"command" : "read-memory",
"response" : [ 0 ],
"status" : {
"description" : "10200 (0x27D8) kStatusMemoryRangeInvalid",
"value" : 10200
}
}

Executing: \blhost -t 5242000 -u 0x15A2,0x0073 -j -- fill-memory 538976256 4 3482320897 word
toolStatus: 0
commandOutput: {
"command" : "fill-memory",
"response" : [],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 50000 -u 0x15A2,0x0073 -j -- configure-memory 9 538976256
toolStatus: 0
commandOutput: {
"command" : "configure-memory",
"response" : [],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 5242000 -u 0x15A2,0x0073 -j -- fill-memory 538976256 4 3221225479 word
toolStatus: 0
commandOutput: {
"command" : "fill-memory",
"response" : [],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 5242000 -u 0x15A2,0x0073 -j -- fill-memory 538976260 4 0 word
toolStatus: 0
commandOutput: {
"command" : "fill-memory",
"response" : [],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 50000 -u 0x15A2,0x0073 -j -- configure-memory 9 538976256
toolStatus: 0
commandOutput: {
"command" : "configure-memory",
"response" : [],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

Executing: \blhost -t 5242000 -u 0x15A2,0x0073 -j -- read-memory 805307392 1024 \vectors\flexspiNorCfg.dat 9
toolStatus: 0
commandOutput: {
"command" : "read-memory",
"response" : [ 1024 ],
"status" : {
"description" : "0 (0x0) Success.",
"value" : 0
}
}

[joogoosa]

After disabling the DCDC and using external Core 1V power nothing seemed to changed but then we realized that it could be the fault of using J-link firmware for the debugger.

After reprogramming debugger with DAP firmware, debugging projects from RAM and erasing flash started to work but debugging from flash seems to not work:

(When starting debug from flash)

MCUXpresso IDE RedlinkMulti Driver v11.5 (Dec 16 2021 12:38:31 - crt_emu_cm_redlink build 2)
Found chip XML file in C:/Users/xyz/Documents/MCUXpressoIDE_11.5.0_7232/workspace/evkmimxrt1170_iled_blinky_cm7/Debug\MIMXRT1176xxxxx.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
============= SCRIPT: RT1170_connect_M7_wake_M4.scp =============
RT1170 Connect M7 and Wake M4 Script
DpID = 6BA02477
APID = 0x84770001
Setting M4 spin code
Setting M4 clock
Resetting M4 core
View cores on the DAP AP
DpID = 6BA02477
TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003*
TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003
============= END SCRIPT ========================================
Probe Firmware: LPC-LINK2 CMSIS-DAP V5.361 (NXP Semiconductors)
Serial Number: GRAUCQKQ
VID:PID: 1FC9:0090
USB Path: \\?\hid#vid_1fc9&pid_0090&mi_00#7&238229c1&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}
Using memory from core 0 after searching for a good core
debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0
processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000C27. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FD000: CID B105100D PID 000008E88C ROM (type 0x1)
ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM (type 0x1)
ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM (type 0x1)
ROM 3 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0)
ROM 3 E0001000: CID B105E00D PID 04000BB002 Gen DWT (type 0x0)
ROM 3 E0002000: CID B105E00D PID 04000BB00E Gen (type 0x0)
ROM 3 E0000000: CID B105E00D PID 04000BB001 Gen ITM (type 0x0)
ROM 2 E0041000: CID B105900D PID 04001BB975 CSt ARM ETMv4.0 type 0x13 Trace Source - Core
ROM 2 E0042000: CID B105900D PID 04004BB906 CSt type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0043000: CID B105900D PID 04001BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router
NXP: MIMXRT1176xxxxx
DAP stride is 1024 bytes (256 words)
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1170_SFDP_MXIC_OPI.cfx
Image 'iMXRT1170_FlexSPI_SFDP_MXIC_OPI Dec 16 2021 12:43:47'
Opening flash driver MIMXRT1170_SFDP_MXIC_OPI.cfx
Sending VECTRESET to run flash driver
Flash variant 'iMXRT1170_FlexSPI_SFDP_MXIC_OPI Dec 16 2021 12:43:47' detected (64MB = 1024*64K at 0x30000000)
Closing flash driver MIMXRT1170_SFDP_MXIC_OPI.cfx
Connected: was_reset=false. was_stopped=true
Awaiting telnet connection to port 3331 ...
GDB nonstop mode enabled
Opening flash driver MIMXRT1170_SFDP_MXIC_OPI.cfx (already resident)
Sending VECTRESET to run flash driver
Flash variant 'iMXRT1170_FlexSPI_SFDP_MXIC_OPI Dec 16 2021 12:43:47' detected (64MB = 1024*64K at 0x30000000)
Writing 35404 bytes to address 0x30000000 in Flash
30004000 done 46% (16384 out of 35404)
30008000 done 92% (32768 out of 35404)
3000C000 done 100% (49152 out of 35404)
Sectors written: 1, unchanged: 0, total: 1
Erased/Wrote sector 0-0 with 35404 bytes in 670msec
Closing flash driver MIMXRT1170_SFDP_MXIC_OPI.cfx
Flash Write Done
Flash Program Summary: 35404 bytes in 0.67 seconds (51.60 KB/sec)
============= SCRIPT: RT1170_reset.scp =============
SYSTEM Reset
DpID = 6BA02477
APID = 0x84770001
Setting M4 spin code
Setting M4 clock
Resetting M4 core
Releasing M4
View cores on the DAP AP
DpID = 6BA02477
TAP 0: 6BA02477 Core 0: M7 APID: 84770001 ROM Table: E00FD003*
TAP 0: 6BA02477 Core 1: M4 APID: 24770011 ROM Table: E00FF003
R15 = 0x00223104
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Error: Wire Ack Fault - target connected?
Vector table SP/PC is the reset context.
PC = 0x001170B0
SP = 0x001170B0
XPSR = 0x01000000
VTOR = 0x30002000
Error: Wire Ack Fault - target connected?
Set DEMCR = 0x011177F1
Error: Wire Ack Fault - target connected?
============= END SCRIPT ===========================
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access
following reset read of core registers failed - Ep(08). Cannot access core regs when target running.
Target error from Commit Flash write: Ep(08). Cannot access core regs when target running.
GDB stub (C:\nxp\MCUXpressoIDE_11.5.0_7232\ide\plugins\com.nxp.mcuxpresso.tools.bin.win32_11.5.0.202112161150\binaries\crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB.
state - running or following reset request - re-read of state failed - rc Nn(05). Wire ACK Fault in DAP access

[jeremyzhou]

Hi，

Thanks for your reply.
I'm glad to hear to you got some progress, to implement debugging in the Octal Flash, it needs to adjust the default flash driver and please refer to the post to make it.
TIC

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[jeremyzhou]

Hi,
Thanks for your clarification.
1) According to the MCU Boot Utility testing log, it seems that the MX25UM51345G connecting circuit is good, and did the MCU Boot Utility tool program the image to the customize board successfully?
2) To debug the code in the MX25UM51345G, it needs to adjust the FCB to fit it, furthermore, it also needs to modify the flash driver of the Jlink, did you already finish them?

Have a great day,
TIC

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- We are following threads for 7 weeks after the last post, later replies are ignored
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[jeremyzhou]

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
After having a brief review of the customize board, firstly, I've not found the connection of MX25UM51345G, then, it should use the 3.3 V to connect the DCDC_IN.

In my opinion, you'd better list the differences versus the MIMXRT1170-EVK, it can help me to figure out the issue efficiently.
I can't judge the configuration of the boot setting, as I have no idea about the connection of MX25UM51345G.
In a word, I need more information.

Have a great day,
TIC

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Note:
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- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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[joogoosa]

Thank you for the quick reply!
It appears that DCDC_IN is a priority issue and we're now devising a temporary fix by disabling the DCDC and powering VDD_SOC_IN externaly.

It's interesting that the DCDC outputs 1V regardless of incorrect input voltage but I'm sure there may be other resulting issues.

Regarding the MX25UM51345G, it is the U7 which originally was intended to be S26KS512SDPBHA020 has been replaced with MX25UM51345G.

[HMUser]

Hi @joogoosa ,

Are you able to solve the issue?

If Yes, could you please let us know the solution.

We are also facing the similar issue with octal flash.