iMX93 : GPIO Read/Write Timings

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iMX93 : GPIO Read/Write Timings

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pratibha
Contributor I

Hi 

I am exploring iMX93 Application Processor.

In which I have some queries regarding GPIO:

  1. How many clock cycles are required to read a GPIO from CM33 and A55 core?
  2. Can we read multiple GPIOs parallel?
  3. And how much approximate time required to read a GPIO?

In refrence manual, in GPIO section 

"28.3.5 Clocking
GPIO receives a single clock, which is used for register access and synchronization with external pin inputs. There are no special considerations."

What does above sentence represents ?

Regards,

Pratibha

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi

For all available module timing, please refer  4.8 System modules timing and 4.6 I/O AC parameters in datasheet

https://www.nxp.com.cn/docs/en/data-sheet/IMX93XEC.pdf

Best Regards
Zhiming

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pratibha
Contributor I

Hi Zhiming,

Thank you for the response. I had referred "4.8 System modules timing and 4.6 I/O AC parameters in datasheet".

In 4.6 section, output transition and rise/fall time given for GPIO. Whereas our main requirement is calculate the GPIO read access time using ARM Cortex-M33.

pratibha_0-1724160778156.png

 

Please provide the information of number of clock cycles required to read the GPIO from ARM Cortex-M33.

Thanks,

Pratibha

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