iMX8QXP Bare metal Cortex m4 cache initialization

[david_binet]

Hi, 

I'm currently working on a baremetal application on the M4 inside the i.MX8QXP and I'm having issues activating the cache. I would like to make sure I'm not missing any steps. I based my configuration of the MPU and cache on the  configuration found in FreeRTOS_BSP_1.0.1_IMX7D. The application code and data are in DDR at 0x8000_0000. Here are the configuration steps:

1. Configure MPU:
   1. Disable MPU in MPU CTRL (bit enable)
   2. Select region 0 with RNR
   3. Configure base address 0x8000_0000 in RBAR
   4. Apply the following configuration in RASR (0x030B003D):
      1. Enable Instruction Access;
      2. Full Data Access Permission;
      3. Write Back, Write Allocate;
      4. Region Not Shared;
      5. All Sub-Region Enable;
      6. MPU Protection Region size = 2GB;
      7. Enable Region 0.
   5. Enable MPU in MPU CTRL (bit enable)
   6. dsb/isb
2. Enable cache in CCR
   1. Write 0x8500_0003 to CCR based on section 12.2.5.3.6.1 Cache set commands of IMX8DQXP reference manual. I noticed that this step was not in FreeRTOS for the iMX7. Is it normal ?
3.  Configure PSCCR
   1. Set invw1 and invw0 in PSCCR register
   2. Set go in PSCCR 
   3. I noticed that the bit go is never set back to 0 as expected in FreeRTOS code.
   4. Set ENWRBUF and enable in PSCCR
4. Configure PCCCR
   1. Set invw1 and invw0 in PCCCR register
   2. Set go in PCCCR 
   3. I noticed that the bit go is never set back to 0 as expected in FreeRTOS code.
   4. Set ENWRBUF and enable in PCCCR

Is there any steps that I'm missing to enable the cache properly ? If you need any more information please feel free to ask.

Thanks for your support,

David

[Yuri]

Hello,

  Use the SDK as code examples.

Welcome | MCUXpresso SDK Builder 

https://mcuxpresso.nxp.com/en/select 

Regards,

Yuri.

[Saravanans1]

Hi,

Will IMx8QxP support the Baremetal application? If it supports please share the document of the IMX8QxP Baremetal user guide or any other reference document.

Regards & Thank You,

Saravanan Shanmugam

[david_binet]

Hi Yuri,

Thanks for the quick response. I had an issue in the initialisation of the LMEM controller. I still have a few questions about the overall operation of the M4.

1. I don't see a write to the CCR like mentionned in the IMX8DQXP reference manual. Is that step still necessary for proper operation ?
2. I'm not sure I understand how the Code cache and the System Cache operate. If I execute code in the DDR (0x8000_0000) will the code cache be used ? Or is the code cache only used when an access is made through the Processor code bus (0x0000_0000 to 0x1FFF_FFFF) ? Is it the same behaviour for the system cache ?
3. Is the system cache an instruction and data cache ? 

From the reference manual it is explicitly mentioned that the code cache is both an instruction and data cache. 

Thanks for your support, I really appreciate it

David 

[Yuri]

Hello,

   Please look at my comments below.

  Based on i.MX8X RM (IMX8DQXPRM, Rev. 0, 05/2020):
Low-order addresses (0x0000_0000 - 0x1FFF_FFFF) use the Processor Code (PC) bus,
and high-order addresses (0x2000_0000 - 0xFFFF_FFFF) use the Processor System (PS) bus.
Normal operation has code accesses on the PC bus and data accesses on the PS bus.
  Chapter 2 (Memory Map) of the RM provides information, what devices / addresses
can be accessed via PC and PS buses. All accesses, that are not mapped to corresponding
TCM are intended for the cache controllers:  
  Processor Code accesses are routed to the SRAM_L if they are mapped to that space.
All other PC accesses are routed to the Code Cache Memory Controller. This controller
then processes the cacheable accesses as needed, while bypassing the non-cacheable, cache
write-through, cache miss ...
 Processor Space accesses are routed to the SRAM_U if they are mapped to that space.
All other PS accesses are routed to the PS Cache Memory Controller. This controller then
processes the cacheable accesses as needed, while bypassing the non-cacheable, cache
write-through, cache miss ...

  To enable / disable the caches LMEM_PCCCR[ENCACHE] and / or  LMEM_PSCCR[ENCACHE]
should be set / cleared.

Regards,

Yuri.

[david_binet]

Hi Yuri,

Thanks for the detailed answer. I ran some tests and the results matched exactly what you explained. Thanks a lot for your support.

Kind Regards,

David