iMX8M Plus: MCLK2 select clock on SAI[x] interface

[ad-fsdev]

Hello,

I am trying to enable one of MCLK2 select clocks e.g. on SAI1 interface and don't see any clocks on SAI1_MCLK pin. Default I am using MCLK1 with SAI1_CLK_ROOT clock and it is working. But if I am trying to change CKKEN0 and SAI1_MCLK_SEL registers to enable SAI1_CLK_ROOT on SAI1_MCKL2 then it does't work. I use memtool from Yocto package imx-test to set relevat bits in the AUDIO BKL_CTRL and SAI1 registers. According to the figure 14-4 from ref. man. IMX8MPRM Rev.1, 06/2021 it should be possible to activate MCLK1-3.

I am using rel_imx_5.4.70_2.3.2 based Yocto BSP.

Do you have any ideas or maybe one example how I can enable e.g. SAI1_MCLK2 clock.

Thank you.

[weidong_sun · Accepted solution]

Hi,

  It means that only MCLK[1] can be routed out to CPU pad(SAI1_MCLK).

 So MCLK[2]  is only used for internal SAI module.

Have a nice day!

Regards,

weidong

[ad-fsdev]

Hello,

thank you.

[weidong_sun]

Hi,

See the following descriptions in Reference Manual, please!

---------------------------------

14.1.1.1 SAI Master Clock Inputs/Outputs
The MCLK pin on each SAI module can be configured as either an input or an output.
When configured as an output, the SAIn_CLK_ROOT from the CCM or the
MCLK_OUT from SAIn is routed to the pad output. Note that the SAIn_MCLK_OUT is
always derived from the ipg_clk_sai_mclk (MCLK[1]) input. When configured as an
input, the external input to the pad will be used as SAIn_MCLK and is routed to
SAIn_MCLK_IN, which can be used as master clock for SAI.

------------------------------------------------------------------------

It means that only MCLK[1] can be routed to SAI1_MCLK pad.

Have a nice day!

regards,

weidong

[ad-fsdev]

Hello,

thank you for your reply. Would you please confirm some statemans bellow for better understanding from my site.

1) Is the SAIn_MCLK_OUT a out clock from blue block figure 14-4 in ref. man?

2) So if I understand you correctly it is not possiblle to route SAI1_CLK_ROOT or other SAI[x]_CLK_ROOT over SAI1_MCLK_SEL[MCLK2_SEL] multiplexer with enabled CLK_EN[SAI1_MCLK2] (disabled CLK_EN0[SAI1_MCLK1]) as output clock from SAI1 blue block figure 14-4 in ref. man.

Thank you again for your time.

Best regards