iMX8M PCIe Reference Clock

[user4567]

The datasheet for the PCIE reference clock input specifies a max cycle to cycle jitter of 35ps.  

The hardware developers guide indicates using the IDT 9FGV0241 will work in this application

However, this datasheet's maximum cycle to cycle jitter is specified at 50ps

35ps seems like a pretty tight spec based on looking at some other PCIe parts, so I assume it has been specified because something breaks when jitter gets beyond that.

What happens to the PCIe link if the jitter spec is violated (how was that spec determined)?

[user4567]

Yes, that makes sense.  I really should be looking to make sure the filtered jitter parameters for whatever PCIe generation I am using match the requirements.  

However, it is not clear to me what the datasheet (table 18) is requiring.  The "DJREF_CLK" requirement is 35ps, and the condition is "DJ across all frequencies", which I assume means deterministic jitter across all frequencies.  So whatever clock I pick requires that the deterministic cycle to cycle jitter be <35ps.  I haven't seen clock ICs that specify deterministic cycle to cycle jitter, rather it is just cycle to cycle jitter..some of which I assume is random and some of which I assume is deterministic.  

Can you explain what this requirement is telling me to look for in a reference clock?

[igorpadykov]

one can look at various Deterministic Jitter presentations:

http://www.ieee802.org/3/ba/public/jan09/li_01_0109.pdf 

Various types of jitter are described on presentation p.16,19:
https://www.keysight.com/upload/cmc_upload/All/ADMF2009_HowToMeasureJitterEffectively.pdf 

Total jitter is composed of Random Jitter (which is unbounded) and Deterministic
Jitter (which is bounded or systematic).  It's specified as peak-to-peak, similar to DJ but since RJ is
Gaussian, it's measured as RMS and extrapolated to peak-to-peak.

Regarding which jitter clock ICs datasheets specifies, one can apply to tech support of vendors these ICs.

Best regards
igor

[igorpadykov]

Hi nathan

seem there is no one figure for jitter and it is complex,

one can look at pcie reference clock jitter description at various app notes, like

https://www.silabs.com/documents/public/application-notes/AN562.pdf 

As described in Hardware Guide NXP EVK board design uses a IDT  9FGV0241 device.

The particular device should support the all specs (jitter, accuracy, etc.).

Best regards
igor
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[user4567]

Perhaps this 35ps spec should be typical, not max? 

I've done a search of PCIe clock generators, 35ps typical is fairly easy to find with 50ps max.  I've only found 1 that will meet this 35ps max and it is not spread spectrum.