I have two questions about the iMX8M RPA LPDDR4 calculation sheet.
1) In the DDRC_INIT7 register the LPDDR4 MR22: ODTE-CS field is set to '1'. If I'm correct than this means that the ODT is disabled for the CS signal in the LPDDR4 device.
What is the reason to only disable the ODT for the CS signals?
2) I discovered that the maximum row address setting for the iMX8M is 16. this means that a single rank memory configuration is limited to 8Gbit per channel. This limitation is not described in the documentation and in the RPA calculation sheet. can this be added?
