iMX7S clock inputs / outputs

[andpas]

Hello,

we are going to design a board with iMX7S, we need to connect clock inputs / outputs to other devices.

While reading the CCM chapter on IMX7SRM the clock structure is quite clear to me,

it's not completely clear to me how the internal signals are connected to external pins.

Referring to signal names used in drawings at pages 496-799, there's not exact matching with pin names at

pages 479-480.

Furthermore, CCM_CLK1_P/N and CCM_CLK2 are not present at all...

Please complete / correct the following connection table:

PIN (direction)  <---> SIGNAL

CCM_CLK1_P / CCM_CLK1_N (input / output) <---> ?

CCM_CLK2 (output) <---> ?

CCM_CLKO1 (output) <---> CCM_CLKO1 

CCM_CLKO2 (output) <---> CCM_CLKO2

CCM_ENET1_REF_CLK (output) <---> ?

CCM_ENET2_REF_CLK (output) <---> ?

CCM_ENET3_REF_CLK (output) <---> ?

CCM_EXT_CLK1 (input) <---> CCM_EXT_CLK1

CCM_EXT_CLK2 (input) <---> CCM_EXT_CLK2

CCM_EXT_CLK3 (input) <---> CCM_EXT_CLK3

CCM_EXT_CLK4 (input) <---> CCM_EXT_CLK4

NOTE: In another post CCM_CLK2 is defined as input only... what is correct?

Thanks

Andrea

[art]

The Section 5.1.3.3 of the RM says the following.

"There are two dedicated IO ports on the chip used for clock generation:

• CLK1P/N: LVDS low jitter differential I/O ports for input or output clocks.
• CLK2: single-ended IO port for input or output clocks.

Both CLK1P/N and CLK2 can take input clocks from outside of the SoC and provide them to the PLLs or to the other modules, or they can take the outputs of the PLLs and provide them outside of the SoC as a functional or reference clock."

ENETx_REF_CLK signals can operate as either inputs or outputs and take the reference clocks for ENET modules from either internal or external clock sources.

CLKO1 and CLKO2 are the general-purpose clock outputs to provide the clocks from various internal clock sources to outside the chip.

EXT_CLKx are the general-purpose clock inputs to provide the functional clocks to various SoC peripherals from outside the chip.

For details of these clock routing settings, please refer to the Table 5-11 of the RM.

Have a great day,
Artur

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[andpas]

Hello,

thanks for the answer.

I read this chapter, but my doubts still remain...

• CLK1P/N + CLK2

While CLK1 should be I/O, CLK2 should be input only (from another post in this forum).
Where are connected these signals? In schematics at pages 495-499 there's no sign of them.

How should I configure them?

• CCM_ENET1_REF_CLK / CCM_ENET2_REF_CLK / CCM_ENET3_REF_CLK

These signals appear to be output only to me. Could you confirm this?

Where are connected these signals? In schematics at pages 495-499 there's no sign of them.

I suppose they are derived from interbal signals ENET1_REF_CLK_ROOT or ENET2_REF_CLK_ROOT or ENET_PHY_REF_CLK_ROOT, but there's no explanation at all about this.

How should I configure them?

Thanks

Andrea