iMX7D: Simulating LPDDR3 with Hyperlynx

[noeliascotti80]

I am doing pre-layout simulation in order to start the PCB design, but I have doubts.
1. I don't find the recommended trace impedance for the LPDDR3 memory in the hardware development guide. The recommended value is only for DDR3 memory, not for LPDDR3. Micron recommends 60 ohm for single ended and 120 ohm for differential pairs. Which value is the correct impedance for LPDDR3 memory?
2. The iMX7 IBIS model doesn't have the Diff pin section, it is a problem for the DDR simulation. Do you have a complete model? We added the diff pin section manually but I don't know if it is fine. I don't know the vdiff value.

[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
AF25 AE25 0.000V 0.000s NA NA
AG23 AG24 0.000V 0.000s NA NA
AC20 AB20 0.000V 0.000s NA NA
AD27 AC27 0.000V 0.000s NA NA
Y24 Y23 0.000V 0.000s NA NA

Thanks!

[noeliascotti80]

My case has never been answered.

- In the recent Hardware Guide there is no special recommendation for LPDDR3 memory. I think it is not the same routing DDR3 or LPDDR3.

- IBIS model does support differential signals. I don't understand why the iMX7 model does not have diff pin section. iMX6 model has diff pin section.

Thanks!

[Yuri]

Hello,

   Please look at Table 19 (DDR trace routing guidelines) of Hardware

Development Guide for i.MX7Dual and 7Solo Applications Processors,

Rev. 1, 07/2017.

Regards,

Yuri.

[igorpadykov]

Hi Noelia

seems this was already answered on ticket:

-recommended to follow memory  rules, published in the recent Hardware Guide

 http://www.nxp.com/assets/documents/data/en/user-guides/IMX7DSHDG.pdf

- IBIS model does not support differential signals. One of possible approach is
to treat with differential signals using single-ended data.

Best regards
igor
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