I.MX7D LPDDR3 measurement issue

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I.MX7D LPDDR3 measurement issue

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frankyhsu
Contributor III

Hi support,

We tried to measure the DRAM timing with 12GHz differential probe. It seems we have the similar problem on the measurement like the problem as below link. But in our schematic, the JTAG_MOD has been pulled down.

Our problem is that when we connect the DQS0 to the scope, the boot will hand up or can not boot, but connect the clock and DQ only without DQS connection can be ok to run the test. Once we connect the DQS, the boot will be fail. I have run the memtool and the stress test can be more than 620MHz, I think the timing tolerance should be enough. Do you have any idea for it?

I want to upload my schematic for you, can anyone see it here? I want to keep it confidential.

https://community.nxp.com/message/913108 

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

 You mentioned, that the DDR Stress test is working.

Are the same DDR initialization parameters used for the Stress testmemory init script and for system boot ?

  Please look at Chapter 1 (Porting U-Boot from an i.MX 6/7 Reference Board to an i.MX 6/7 Custom Board) of “i.MX_BSP_Porting_Guide.pdf”

 

 http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.1.0_LINUX_DOCS&Parent_nodeId=133769948107170617... 

Have a great day,
Yuri

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frankyhsu
Contributor III

I mean when I perform the DDR timing test in scope to measure the timing, it will cause boot fail or hand up. The parameter we used can support the stress test up to 6xxMHz, the tolerance should be enough.

I have checked the waveform of the DQS, the write waveform for DQS is good but we found the read waveform is very ugly. The Read DQS comes from the LPDDR3 and the measured point is on the carrier of the LPDDR3. Do you have any idea for it? I know the LPDDR3 on IMX7 does not support the ODT. Or we need to measure the read DQS on the CPU (receiver) side?

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frankyhsu
Contributor III

The read waveform is as below, the DQS is output from LPDDR3 and measure on the LPDDR3 carrier test package.

Read_DQS-DQ.bmp

The below is the write and output from IMX7D, the measure on the LPDDR3 carrier test package.

tDS_WRITE.bmp

Since the write waveform is good, so I think the PCB impedance should be ok but we get the bad output from the LPDDR3. From your experience, what can we try from the PHY setting?

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  You may try to configure DDR drive strength.

Regards,

Yuri.

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