iMX6UL Power Management and clock control module (CCM)

[joe_dougherty]

In trying to reduce power consumption on iMX6UL using clock gating control in the CCM, some of the clocks are not well defined in the reference manual (IMX6ULRMRev. 1, 04/2016) Can anyone clarify what the following clocks do? Refer to Chapter 18 of the reference manual.

CCM_CCRG6 .CG11 - anadig clocks (anadig_clk_enable). Assume for ADC module but not referenced in ADC chapter. Search of “anadig” in RM doesn’t show much.

CCM_CGR5.CG1 - stcr clock (stcr_clk_enable). Search of “stcr” doesn’t show much. Assume this is audio related.

CCM_CGR4.CG4 - cxapbsyncbridge slave clock (cxapbsyncbridge_slave_clk_enable) – Nothing in RM.

CCM_CGR5.CG8 - sim_main clock (sim_main_clk_enable) – Nothing in RM

CCM_CGR1.CG9 - sim_s clock (sim_s_clk_enable) - Nothing in

[igorpadykov · Accepted solution]

Hi Joe

anadig clocks are for CCM_ANALOG part (sect.18.7 CCM Analog  RM)

stcr clock for spdif (Chapter 48 Sony/Philips Digital Interface (SPDIF))

cxapbsyncbridge (Chapter 15 AHB-to-APBH Bridge)

sim_main clock, sim_s clock (Chapter 44 Subscriber Identification Module (SIM))

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------