I’m using an iMX6Q processor (bare metal build) and am trying to determine the correct usage of the IPU_CH_BUF0_RDY and IPU_CH_BUF1_RDY bits in the IPU. I’m using a single buffer for a (static) background (IDMA ch 23), and double –buffering the foreground (ch 27). Now let’s say I’m displaying BUF0 (EBA0), IPU_CH_BUF0_RDY0:27 is 1, IPU_CUR_BUF:27 is 0, and I’m updating BUF1 (EBA1). It takes me several display refresh cycles (@ 60 per secs), say 60ms, to update BUF1 with new data. Now I want to switch over to display BUF1 (and then update BUF0) – which of course is the purpose of double buffering. If I now set IPU_CH_BUF1_RDY0:27 to 1, will this cause a switch to display BUF1 at the next EOF (so I can update BUF0)? I can’t clear IPU_CH_BUF0_RDY:27 using software, so how does it get cleared if the displays are swapped?
I tried playing around with the registers using a probe. I can set IPU_CH_BUF0_RDY0:27 fine. I thought if I then set IPU_CH_BUF1_RDY0:27, that it would clear IPU_CH_BUF0_RDY0:27, but it doesn’t, both bits remain set. This is with the IPU not running, so things may be different when it’s active. Any insight?
Hello,
You can read the Mx6 reference manual for more information and you can how it is on current driver in yocto BSP.
Regards