iMX6DL : How to set the PCIe PHY Reference Clock source ?

[koichisakagami]

Dear community,

I consider using i.MX6DL PCIe PHY
Please see Table 50-1 (p.4455) in IMX6SDLRM (Rev.1).

I hope use the  CLK1(In)  to "Reference Clock" as a clock source
with the following setting.

Is my understanding correct ?

CCM_ANALOG_PLL_ENETn (pp.909-911)
  ENABLE_100M：0x1
  BYPASS_CLK_SRC：0x1
  BYPASS：0x1

PMU_MISC1n (pp.4528-4530)
  LVDSCLK1_IBEN：0x1
  LVDSCLK1_OBEN：0x0

PCIE_PHY_MPLL_ASIC_IN (pp.4470-4471)
  MPLL_MULTIPLIER：0x19

PCIE_PHY_ATEOBRD_STATUS (pp.4474-4475)
  REF_CLKDIV2_IN：0x0

If some adittional setting is required, could you let me know it ?

Best Regards,
Koichi Sakagami

[igorpadykov · Accepted solution]

Hi koichi

I think that understanding is correct and

these settings are sufficient for external clock.

Also one can refer to example below

i.MX6Q: Using an external reference for PCIe

Best regards

igor

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[koichisakagami]

Dear igor san,

With the following setting,
does the CLK2(out) output the  "Reference Clock"  ?

PMU_MISC1n (pp.4528-4530)
  LVDS2_CLK_SEL : 0b01010 (PCIE_REF)

"Reference Clock" is defined at

Table 50-1 (p.4455) in IMX6SDLRM (Rev.1).

Best Regards,

Koichi Sakagami