iMX6: how to trigger software reset

[rafalwegner]

Hello

Does anyone knows and could describe the procedure of how to trigger a reset of the board (power off / power on) from software (u-boot application)?

I believe some of the SRC registers should be configured properly to obtain such behaviour.

Thanks very much in advance

BR, Rafal

[Embedded-world]

Hi @JithCR @AnsonHuang @rafalwegner @mrleo 

Regarding the statement you mentioned, 'If you use the "reboot" command in the kernel, the PMIC (PFuze) will also be reset by our watchdog reset, which will result in a power off/on reset.'

As you mentioned the above statement, the "reboot" command is not working in our case (board), and we've assigned the watch_b signal to the LCD_REST pin in our imx6ull SOM with baord. I've also referred to previous watchdog posts, but still, it's not rebooting the board. Please help us with this issue.

How can I modify the watchdog node in the dts file for reboot? 

Thank you & Regards,
Ravikumar

[AnsonHuang]

Hi, Rafal

     Do you mean the command of uboot to reboot the board? If yes, you can use "reset" command in uboot to reboot system, the eventual operation of "reset" command will trigger a wdog reset which will reboot i.MX6 SOC. But it will not reset the PMIC, so it is not a power off/on reset, it only reset our i.MX6 SOC.

     If you use "reboot" command in kernel, the PMIC(PFuze) will be also reset by our wdog reset, which will be a power off/on reset.

     So, in a word, in uboot, "reset" is to only reset our i.MX6 SOC, in kernel, "reboot" will reset both our i.MX6 SOC and external PMIC which connect its reset pin to our WDOG_B pin.

[zlhuang]

Dear Yongcai,

     I have several boards of the same hardware based on mx6dl-sabresd.

     When I use "reset" command in u-boot, some boards reset from [WDOG ], but others always reset from [POR ].

     I have no idea how to debug and fix it. Could you give your opinion?

     Thanks.

BRs,

ZL

[AnsonHuang]

Hi, ZL

     Because in uboot, we only trigger wdog reset, and in kernel, when wdog reset, we enable it to output a wdog_b signal which will be connected to PMIC, and cause the whole board power down and power up again, that is why you get POR reset in kernel, but get WDOG in uboot.

[zlhuang]

Dear Yongcai,

     I got [POR ] after using "reset" command in u-boot on some of my boards

      Is this reasonable? Or it's hardware issue?

     Thanks.

BRs,

ZL.

[AnsonHuang]

You can monitor the POR pin on i.MX6, the only reason of getting POR reset reason of that there is toggling on this pin.

[zlhuang]

Dear Yongcai,

     Our board config WDOG2 to be the output (MX6DL_PAD_GPIO_1__WDOG2_WDOG_B) and connects it to POR.

     When I config WDOG1 to generate wdog_reset, I measured that the WDOG_B is also asserted.

      That's why the reset reason is POR.

      Could you help? Thanks.

BRs,

ZL

[AnsonHuang]

You can just disable the wdog_b signal when you config wdog1 to reset.

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iMX6: how to trigger software reset

reply from ZL Huang<https://community.freescale.com/people/zlhuang?et=watches.email.thread> in i.MX Community - View the full discussion<https://community.freescale.com/message/391480?et=watches.email.thread#391480>

[zlhuang]

    I have tried to set WDOG2_WCR to 0xF3, but it does not work.

    Could you suggest how to disable WDOG_B signal?

    Thank you very much.

[AnsonHuang]

If you want to not trigger WDOG_B signal, please write 0x4 to WCR to issue a wdog reset. If you want to trigger WDOG_B, using 0x14 instead.

You can try it.

The other option is just modify the IOMUX setting of WDOG_B MUX, set it to be other function.

[JithCR]

Dear Yongcai,

Is it okay to configure WCR with 0x14 in disabled LDO bypass mode (ie LDO enabled mode)?

Regards,

Jith

[zlhuang]

Dear Yongcai,

     Our board config WDOG2 to be the output (MX6DL_PAD_GPIO_1__WDOG2_WDOG_B).

     However, when I write 0x4 to WDOG1_WCR t to generate wdog_reset, I measured that the WDOG_B is also asserted.

     I don't know if it is normal.

    What should I do to disabe WDOG_B signal ( from WDOG2) before I generate WDOG1 wdog_reset?

BRs,

ZL

[AnsonHuang]

This pin is also related to the board design, for example, when SOC is reset, this pin’s default state may also change, copy Gong Yibin.

Best Regards.

Anson Huang

Freescale Semiconductor Shanghai

Tel:021-28937058

[zlhuang]

Dear Yongcai,

      Do you mean we cannot disable the WDOG_B signal by software?

      Thanks.

BRs,

ZL

[AnsonHuang]

No, I meant you can disable WDOG_B pin function, such as set it to be other function, then trigger wdog reset by writting 0x4, then measure this pin to see whether it is asserted when wdog reset the system.

[zlhuang]

Dear Yongcai,

     Because I need the WDOG_B signal( from WDOG2), I cannot disable it.

I just want a simple wdog_reset function from WDOG1.

Thanks anyway.

BRs,

ZL

[AnsonHuang]

I just want to identify the root cause, this is only to see whether it is related to board design, not final solution.

[zlhuang]

I have disabled the WDOG_B pin, but I still measured that the pin is asserted at wdog_reset.

[AnsonHuang]

OK, so that means your board design may not good enough. Can you check your board design of WDOG_B pin, does it has a pull up resistor? WHat value? Can you change it to be less than 10K OHm? then monitor this pin's signal to see whether it still assert when we do a pure wdog reset by writting 0x4 to wdog controller register?

[zlhuang]

The original design has a 100KOhm pull-up resistor, which is alleged reference design from freescale.

We change it to 10KOhm, and it is ok for wdog_reset(WDOG_B is not asserted).

However, it fails for POR reset when we control WDOG_B to be asserted.

The balance value for both POR reset and wdog_reset is 33KOhm.