iMX6 data cache prefetch

[ofer_livny]

Hi

I noticed that the iMX6 cache prefetching is disabled, and then found the erratum on that topic, saying that enabling  prefeching can lead to deadlock or data corruption.

My questions are -

1. I want to enable prefetching, to see how often my application will suffer from this issue. How can I do that? (I'm using iMX6Q running u-boot 2009 and linux 3.0.35_4.1)

I found the ARM documentation regarding ACTLR register (ARM Information Center) but couldn't find the right place to update this value in the u-boot / kernel.

2. When doing some profiling on my DDR I see a big difference between reads and writes - DDR write is more  or less x8 faster than reads. Assuming that data prefetching is disabled - does this difference make sense?

The profiler is doing continuous block reading/writing for blocks larger than the L2 cache.

Thanks,

Ofer

[igorpadykov]

Hi ofer.livny

1. One can add to Uboot lowlevel_init.S or cpu.c,

Uboot structure can be found in

AN4173 U-Boot for i.MX51 Based Designs

2. No data prefetching can affect this. Probably these smth related

to cache settings. Probably it makes sense to check without OS,

using SDK

i.MX 6Series Platform SDK : Bare-metal SDK

Best regards

chip

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