iMX6 ULL ULZ reference design length matching

[oiram]

Hy,

I am doing a design around iMX6 ULZ processor and have downloaded the reference design files from here . I have converted the gerber files to altium pcb file and copied the DRAM traces to my design.

In Altium I have rules set up for matching lengths according to Hardware Development Guide for the i.MX 6ULL Application Processor , specifically the DDR3 routing by byte group as in table below:

But some of the groups from your reference design are not matched to this spec. For examle:

DATA HIGH group is matched within this spec. All signals, including SDQS1 are around 27.1 mm

but

DATA LOW group has data signals lengthmatched to around 25mm but SDQS0 are matched to 30,6mm ... that is more than 4mm diffence, much more than 25mil (0.635mm) spec.

and even more strange are the Address signals

About half of those are 38mm and other half is 35mm

Screenshot_1.png

Now, only explanation would be the board thicknes and via lengths. Have you included the via lengths in your lengths, because 3-5 mm difference seems too much for ddr3. How thick is the board? It just seems strange

[riteshmpatel]

Hi @oiram,

I hope you are doing well.
Apologies for the delay in response.

One can find the board thickness in the Fabrication Layer of the i.MX6ULL EVK. Via lengths are not considered in this.

It is strongly recommended to follow the HDG document.

Thanks & Regards,
Ritesh M Patel

[oiram]

Should I use the via length in my design then? Altium automatically accounts it into the length? The HDG document doesn't say anything about via lengths. It seems strange that your design doesn't use via length

[riteshmpatel]

Hi @oiram,

One can consult with the relevant tool vendor to know if the via lengths are considered or not in the length matching.
Regarding the length matching, NXP strongly recommends following the data given in the HDG document.

Thanks & Regards,
Ritesh M Patel