Hello,
I’m newbie to the embedded world and firmware development. Please excuse me for questions. I’m using iMX6 SOM for my project and one of the requirements for the project is to use SPI in master mode with SPI_RDY. I want SPI Data Ready Control to be level-triggered. Could someone clarify my questions:
- How can I set ECSPI_CONREG[DRCTL] bit from user space?
- I want SPIDEV test application to wait for spi_ready signal and not to timeout (transfer timeout errors). How can I disable or increase the timeout during development testing?
Thanks,
Chaithu
