iMX6_SOLOX_START_UP

[victorafanasiev]

My questions are concerning of powering the microprocessor   iMX6 SOLOX.

1) I am not using of non-volatile features of the iMX6 SOLOX microprocessor. Because of this I would like to combine VDD_HIGH_IN and VDD_SNVS_IN pins of the iMX6 SOLOX microprocessor as proposed in the file IMX6SXAEC.pdf (4.1.3 Operating Ranges Table 10). What a power rail from the preprogrammed PMIC chip MMPF0200F6AEP should I use to power the combined pins VDD_HIGH_IN and VDD_SNVS_IN? I think that I cannot use the output VSNVS_3V0 because it is too weak but I cannot use the output VGEN6_3V0 because it is appeared late to delay the PMIC_PWRON >500ms to ensure 32.768kHz xtal osc output is stable. Is it means that to power the combined pins VDD_HIGH_IN and VDD_SNVS_IN I must use an external LDO connected to the SYS_3V8 net of PMIC   MMPF0200F6AEP?

2) I am confused about the nets PMIC_PWRON and PMIC_ON_REQ of the MCIMX6SX SDB board (SCH-27962 PDF: SPF-27962, the file SPF-27962.pdf). These two nets are shorted through the resistor R317 (sheet 4). But the net PMIC_PWRON is connected to the output R̅S̅T̅ of the IC U41 and the net PMIC_ON_REQ is connected to the output SNVS_PMIC_ON_REQ of the microprocessor   iMX6 SOLOX. Two outputs are shorted. Is it correct? Is it allowed?

3) I am not use the Android button on my board. How I should connect the pin ONOFF of the microprocessor   iMX6 SOLOX to have automatic Power ON my board when the input voltage is turn ON?

4) I would like not to use the SW2 output of the PMIC as a source of 3.3 volts for my PCB. I plan to use the input voltage 3.3V and a load switch instead of use the SW2 output of the PMIC. If I do not soldered on the board components related to SW2LX, SW2IN, SW2FB pins of the preprogrammed PMIC chip MMPF0200F6AEP, will the preprogrammed MMPF0200F6AEP generate the error and interrupts signals if the SW2_3V3 voltage is absent?  Will the MMPF0200F6AEP start?

[igorpadykov]

Hi Viktor

1. i.MX6SX Sabre SD schematic p.5 SPF-27962.pdf uses solution with

combined VDD_HIGH_IN and VDD_SNVS_IN pins connected to VGEN6.

2. there are no problems in connecting PMIC_PWRON and PMIC_ON_REQ,

I did not find them on i.MX6SX Sabre SD schematic.

3. for unused pins please check sect.2 Pin connection guidelines

AN4751 Schematic Guidelines for MMPF0200

https://www.nxp.com/docs/en/application-note/AN4751.pdf 

Best regards
igor
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[victorafanasiev]

Hi Igor.

Thank you for your replay to my questions. But I need still some clarifications.

About question #1:

I have downloaded the schematic file SCH-27962 PDF: SPF-27962 Rev. C from https://www.nxp.com/webapp/sps/download/preDownload.jsp . This schematic is in the attachment to my letter. As we can see in this version on the sheet 5 the pins VDD_HIGH_IN and VDD_SNVS_IN are connected to different nets: the pin VDD_HIGH_IN is connected to VGEN6_3V0 and the pin VDD_SNVS_IN is connected to VSNVS_3V0. The diode D25 is not soldered. So, the VDD_HIGH_IN and VDD_SNVS_IN pins are not combined. Maybe my version of the schematic is out of date? Can you send me the actual version of i.MX6SX Sabre SDB schematic SPF-27962.pdf?

About question #2:

We can see on the page 4 of the schematic, attached to my letter, nets PMIC_PWRON and PMIC_ON_REQ are combined through resistor R317, situated at the zone A3 of the sheen 4. The resistance of R317 is equal to 0. So, nets PMIC_PWRON and PMIC_ON_REQ are shorted. The net PMIC_PWRON is driven by the output RST of the IC U41 (see sheet 20). The net PMIC_ON_REQ is driven by the output SNVS_PMIC_ON_REQ of the IC U1 (see sheet 6). So, two outputs are shorted. Is it correct? Maybe in the more actual version of i.MX6SX Sabre SDB schematic these nets are not shorted?

About question #3:

What about my question #3?

About question #4:

I have read the application note AN4751. My concerns are due to the fact that PMIC chip MMPF0200F6AEP is preprogrammed. If I am not soldered on the board components related to SW2LX, SW2IN, SW2FB pins than there will be no any voltage on the output on the pin SW2FB of the preprogrammed PMIC MMPF0200F6AEP. Can such situation cause the generation of the error signal by the chip MMPF0200F6AEP?

[igorpadykov]

Hi Viktor

1. since VGEN6_SEQ  "F6" is preprogrammed on step1, so diode D25 can be populated

2. both PMIC_ON_REQ and U41 output RST are open-drain, so two outputs are not shorted

3. ONOFF can be left unconnected

4. it does not matter preprogrammed or not, just follow AN4751

Best regards
igor

[victorafanasiev]

Hi Igor,

I'm sorry to bother you, but hope that you will help me to eliminate my doubts about shorted nets PMIC_PWRON and PMIC_ON_REQ of the MCIMX6SX SDB Board (SCH-27962 PDF: SPF-27962, the file spf-27962. pdf) via the resistor R317. Through the built-in resistor of the pin SNVS_PMIC_ON_REQ of the microprocessor SOLOX these combined circuits are pulled up to the voltage VDD_SNVS_IN. Indeed, as you noted, the output RST of the IC U41 is of open-drain type. But according to the file IMX6SXAEC.pdf, the pin SNVS_PMIC_ON_REQ of the microprocessor is of pure output type. If a customer pressed the Reset button, then the output RST of the IC U41 will go to the low state. At the same time the output SNVS_PMIC_ON_REQ of the microprocessor has the high state. As the result we get an invalid state. Can this lead to a failure of the output SNVS_PMIC_ON_REQ of the microprocessor? Maybe I'm wrong about something?

Victor.

[victorafanasiev]

Hi Igor

Thank you for your replay to my questions.