I’m trying to determine the correct order in initializing the caches and mmu at power up for the iMX6 Quad. This is for a custom OS. This is what I have so far:
_int_disable();
// Disable the mmu if it is enabled (shouldn't be enabled on powerup)
_mmu_disable();
// Disable the icache, dcache and L2 cache
_L1_dcache_disable();
_L1_icache_disable();
if(_l2c310_cache_sts())
_l2c310_disable();
// Invalidate dcache, and L2 cache – what about the icache???
_dcache_invalidate(); // invalidates L1_dcache and L2 cache
// Allocate the memory for the mmu Section Table
L1_TBL_ptr = _mem_alloc_align(MMU_L1_TBL_SIZE, MMU_L1_TBL_ALIGN);
// Clear the mmu table
_mem_zero(L1_TBL_ptr, MMU_L1_TBL_SIZE);
// Initialize the mmu
// - Map all of memory space to 1 MB sections, strongly ordered, RW, shared
// - Remap sections that are actually used – DDR, SRAM
_mmu_init();
// Initialize the mmu
// - Map all of memory space to 1 MB sections, strongly ordered, RW, shared
// - Remap sections that are actually used
_mmu_init();
// Enable the mmu
// - Save the address of the mmu table in the TTBR0
// - Write the DACR register – 0x55555555
// - Invalidate the TLB (including DSB and ISB following)
// - Enable the MMU
_mmu_enable();
DSB;
ISB;
// Enable the caches
_l1_dcache_enable();
_int_enable();
At this point there is a prefetch error, and I can’t get beyond here.
Somewhere up above the sequence of everything is messed up. The mmu is set up flat-mapped; va = pa
Things I don’t know how to put into the sequence:
- Invalidating and enabling the branch prediction cache
- Enabling the dcache prefetch
I’ve looked at the SDK, including the patch to add L2 cache to SDK, however this crashes as well as soon as the dcache is enabled.
Any ideas??
