iMX6 DDR3 Routing on Sabre Dual Lite board

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iMX6 DDR3 Routing on Sabre Dual Lite board

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Contributor II

I have looked at the DDR3 routing on the Sabre Dual Lite reference design and the DDR3 routing rules in the Hardware Development Guide for i.MX6 Dual Lite.

First the length matching of the address and control signals for DDR3 is off by almost 700mil. Below is a table with the traces lengths measured on the reference board.

DRAM_A02366.603
DRAM_A12428.392
DRAM_A22485.718
DRAM_A32485.538
DRAM_A42740.291
DRAM_A52810.391
DRAM_A62815.121
DRAM_A72917.064
DRAM_A82809.252
DRAM_A92511.654
DRAM_A102256.097
DRAM_A112437.487
DRAM_A122481.741
DRAM_A132612.41
DRAM_A142546.543
DRAM_A152399.771
DRAM_CAS_B2235.064
DRAM_CS0_B2394.055
DRAM_RAS_B2286.018
DRAM_RESET_B2952.954
DRAM_SDBA02501.59
DRAM_SDBA12560.122
DRAM_SDBA22326.787
DRAM_SDCKE02235.184
DRAM_SDCLK02086.344
DRAM_SDCLK0_B2080.717
DRAM_SDCLK12113.077
DRAM_SDCLK1_B2113.37
DRAM_SDODT02717.477
DRAM_WE_B2341.702

Look at the different lengths between A7 which is the longest and CAS or CLK0.

Why is the length matching so far off compared to the required +/- 25mil as specified in the Hardware Development Guide.

The length matching of the individual data groups are within 10 mil  for each group.

Appreciate feedback on this because I am using the same concept as reference design but have some concerns about the length matching of address and control signals.

Thanks

Manie

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84 Views
NXP Employee
NXP Employee

Hi Yuri,

You are comparing total trace lengths, and not the trace lengths from point-to-point. This is what really maters. It is the trace length from the processor to each individual DDR3 device.

For example, the trace length for DRAM_A0 from the processor to DDR3 U5 is only 1712.15 mils. If you do all the individual point-to-point calculations yourself, you will see that most of the Address traces come in around 1700 mils. The clock traces are a little trickier because you need to add the DDR_SDCLK trace segment to the DRAM_SDCLK segment.

The Smart Device is actually laid out much better than you might think. There are a few minor areas where the lengths disagree with the recommended guidance. The design was laid out by a third-party and went to production before all the recommended changes from FSL were incorporated. Once the design was approved, management required furture designs to follow this layout with no deviations.

The layout works quite well, and does not require changing if you want to just encorporate it wholly into your design.

Cheers,
Mark

84 Views
Contributor II

Hi Mark,

I have used the layout of Sabre Dual Lite reference design for DDR3 as mentioned above. You are correct that one should look at the point to point net lengths and I could post them if required.

A number of boards are failing DDR3 memory tests when subjected to an operating temperature test of -40C to +85C ambient. It seems that the DDR3 memory calibration is not good enough or there is not enough margin in the design due to nets not being match properly.

The boards work fine at high temperature if calibration was done at around +40C but will fail at low temperatures. Only memory stress testing is done to ignore any other aspects of the hardware.

The first step is to verify that calibration is done correctly because to match the net lengths better will require another board spin.

Are you the correct person to discuss DDR3 memory calibration with.

We are using Application note AN4467, that describes how to do calibration but it will be nice to verify that it is done correctly.

The following calibration order is followed.

1) One-time forced ZQ Calibration

2) Write Leveling Calibration

3) DQS Gating

4) Read data DQS calibration

5) Write data DQS calibration.


Is there anything that we may miss during calibration.

Regards

Manie

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84 Views
NXP TechSupport
NXP TechSupport

Reference schematics are designed simultaneously or earlier design check recommendations.
Therefore example designs may violate some rules of design checklist(s). Also we should take into
account that basically, the best approach - to use simulation technique for PCB design.

In the same time, general rules may be provided for customers to simplify their PCB considerations,

but - for assurance - such rules are very strong.

84 Views
Contributor II

I do follow what you are saying but it does not help me a lot. I am trying to determine what the risk of the Sabre DDR3 layout is to be used in production. This only applies to the length matching of the address and control signals. Can the iMX6 compensate for the length mismatch of 700mil. You mention that one should simulate the PCB layout which is good but this will not remove the length mismatch of 700mil between two signals on the same layer.

The bottom line question for me is to determine what the risk is to use the Sabre board DDR3 layout versus doing it over with proper length matching of address and control signals. it would be sad if I have to do it over because that means the Sabre reference design is worthless as a true reference. 

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84 Views
Contributor II

I have simulated the design and made some changes to routing get the flight times closer to each other at the DDR3 chip.

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