iMX RT1175 FlexCAN Multiple Message/Frame Receiving Issue

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iMX RT1175 FlexCAN Multiple Message/Frame Receiving Issue

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Chetan_Chavan
Contributor II

Hi!

I have an application requirement wherein the master node transmits a CAN frame to a slave node and in return the slave node acknowledges the master by transmitting 5 frames in a burst fashion. 

My problem is that I am unable to receive all the 5 frames. The processor only receives the 1st frame. Initially I used only a single message box to receive all frames but it did not work out as only the 1st frame was being received. Then, I tried configuring 5 different message boxes by setting unique identifiers and masking for each of the frames. Even in such a case, only the 1st frame was being received. I have been "switching" function (for switching state of message buffer from idle to receive) in the ISR itself. 

Lastly, I also tried FIFO concept but even in that I could only receive the 1st frame. The Slave node is sending all 5 frames as I have tested it on other controller. 

If there is any example node similar to my application stated above, kindly share it. Also, I want to know if there is any conceptual missing on my part for handling such a case. Somehow, I feel that the processor is unable to receive frames that are sent in a burst fashion and necessarily require a considerable delay between the frames. Is my understanding correct?

I kindly request you to help me out in this issue.

Regards,

Chetan.

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Chetan_Chavan
Contributor II

Hello Kerry,

We were able to find the solution. There's a bit "Disable Self Reception" in one of the control registers (MCR[SRXDIS]) that was cleared. When we set this bit, we started receiving all frames without any delay at Slave node.

Worked seamlessly!

Thanks for being there and timely suggestions/follow-up. Will reach out to you in case I get stuck anywhere again in the development process.

Best Regards,

Chetan.

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Chetan_Chavan ,

   Do you test the FlexCAN based on the RT1170 SDK, use the interrupt_transfer project or your own write code?

  Do you test this code?

SDK_2_10_0_MIMXRT1170-EVK\boards\evkmimxrt1170\driver_examples\flexcan\interrupt_transfer

   If yes, do you modify it or not? Whether you try one RT1175 board as on CAN node, and other CAN node use the PC side + CAN testing tool, then send 5 frame to the RT board continuously? I think this will help you to test it, as the above code is the interrupt_transfer, so, when receive the code it will generate the interrupt to receive it, my understanding is the 5 frame should have some delay, at least let the previous CAN message is received by the CAN interrupt code.

  So, CAN you do another PC side CAN node, and send the 5 frame data with some delay?

  If you still have issues, please kindly let me know.

Best Regards,

Kerry

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Chetan_Chavan
Contributor II

Hi Kerry!

Thanks for the reply!

Coming to you queries :

Do you test the FlexCAN based on the RT1170 SDK, use the interrupt_transfer project or your own write code?

No, we are using our own custom board and not the SDK. Yes, we have used the interrupt transfer project code itself that has been provided and modified it to receive 5 frames in 5 different message buffers using unique identifier and filtering for each of the frames.

Do you test this code?

Yes, all my statements/observations are based on testing the code.

If yes, do you modify it or not? Whether you try one RT1175 board as on CAN node, and other CAN node use the PC side + CAN testing tool, then send 5 frame to the RT board continuously?

Yes, we modified the interrupt_transfer code as explained earlier. Both the nodes are custom nodes wherein the master node is RT1175 and slave node is a TI DSP controller. I have used Texas instruments' RM57 (uses same message buffers concept as provided by RT1175), TMS570 and NXP's 9s12XDP512 controllers and they all seem to receive the frames properly without any delay. 

In the case of RT1175, whenever the Slave node is adding some delay (say 1ms) in between the 5 frames, I am able to receive all the frames whereas when there's no delay, I only receive the 1st frame continuously! This does not happen for other TI or power PC controllers. 

So is the delay mandatory in the case of RT1175 in between the frames in order to receive all frames correctly? I don't think delay should be an issue because other controllers working at very low clock speeds didn't require so. 

What do you suggest next? 

Regards,

Chetan.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Chetan_Chavan ,

  Thanks for your information: In the case of RT1175, whenever the Slave node is adding some delay (say 1ms) in between the 5 frames, I am able to receive all the frames whereas when there's no delay, I only receive the 1st frame continuously! 

Do you mean, you also try that the RT1175 as both master and slave node, then if the RT1175 node didn't add the delay, RT1175 master just recieve one frames, right?

  If yes, please upload your modified project, both for the master, slave with delay and no delay, I will find time to test it and check the details.

  BTW, please also let me know your used IDE and SDK version, thanks.

  I think this issue is related to the interrupt overflow when more frame send to the master, but I need to check the details.

Best Regards,

kerry

 

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Chetan_Chavan
Contributor II

Hello Kerry,

We were able to find the solution. There's a bit "Disable Self Reception" in one of the control registers (MCR[SRXDIS]) that was cleared. When we set this bit, we started receiving all frames without any delay at Slave node.

Worked seamlessly!

Thanks for being there and timely suggestions/follow-up. Will reach out to you in case I get stuck anywhere again in the development process.

Best Regards,

Chetan.

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Chetan_Chavan ,

Glad to hear you find the solutions, thanks for your effort.

Any new issues, welcome to create the new case.

To this case, please make the correct answer, just to close this case, thanks.

 

Best Regards,

kerry

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