iMX Clock Divider

[raajeshk88]

I am trying to divide a clock (CLKO2) to 12MHz from its default value 24MHz. From imx6qclk.c there is function call to 

clk[IMX6QDL_CLK_CKO2_PODF]  = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);

whatever i change in the bit values (3/4/5 ) the divider is still the same. can someone explain how this clock divider works. Thanks

[igorpadykov]

Hi Raajesh

one can attach jtag and check CCM_CCOSR register, it is described in

sect.18.6.21 CCM Clock Output Source Register (CCM_CCOSR) i.MX6DQ Reference Manual.

Also necessary initialization can be done in uboot. As for dts clock settings may be useful to look on

Where pll4_bypass_src is set to choose osc 24MHz or CLK2_N/P as source in linux BSP code? 

Best regards
igor
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[raajeshk88]

Hi Igor,

         Thanks for the reply. Actually I am looking to use the clk_divider API to divide the clk. From the register settings it says the bits 21 to 23 is for divider (000-111) but i want ot knwo to set 101 for the bits 21-23 using this API. 

[igorpadykov]

Hi Raajesh

for example one can try to change "mclk" to necessary value

ov564x: ov564x@3c {..
clocks = <&clks IMX6QDL_CLK_CKO>;
..
mclk = <24000000>;

imx6qdl-sabresd.dtsi\dts\boot\arm\arch - linux-imx - i.MX Linux kernel 

Best regards
igor