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Where pll4_bypass_src is set to choose osc 24MHz or CLK2_N/P as source in linux BSP code?

Question asked by 磊 葛 on Jun 1, 2017
Latest reply on Jun 6, 2017 by 磊 葛

Hi NXP engineers,

On the 6qp_sabreauto board, ESAI use 24.576Mhz external osc as clock source,and the clock route is like this:

In the kernel code, only esai_sel is set by imx6qdl_sabreauto.dtsi to choose 'PLL4 divide clock':

 

I didn't see where pll4_bypass_src is set in the BSP code:

We need to use 24MHz osc as pll4 source,so we need to know where pll4_bypass_src is set in the BSP code(but we can't find related code).

Can someone explain this in detail? Lily Zhang li qiang

 

Thanks! 

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