Hi NXP engineers,
On the 6qp_sabreauto board, ESAI use 24.576Mhz external osc as clock source,and the clock route is like this:
In the kernel code, only esai_sel is set by imx6qdl_sabreauto.dtsi to choose 'PLL4 divide clock':
I didn't see where pll4_bypass_src is set in the BSP code:
We need to use 24MHz osc as pll4 source，so we need to know where pll4_bypass_src is set in the BSP code(but we can't find related code).