i.mx9 using flexio to generate an interrupt and general question about interrupts in multiple cores

[Vitus]

There will be a setup of the iMX9 with Linux on the A55 cores and FreeRTOS on the M33 core. I currently do initial stuff on the M33.

Question 1:

for a magnetic pickup sensor (frequency sensor) I need an simple interrupt generated from a FlexIO pin. In the interrupt I will read the value of a CPU internal timer and calcucate so the pickup frequency.  (This already works with a GPO interrupt). In a NXP Sdk (SDK_2_15_000_MIMX9322xxxxM) I found some examples for Uart, SPI and I2C receive and interrupts, but they are much to complex for my purposes. Is there a simple example for just  an interrupt generated by FlexIO? 

Question 2:

if a GPIO or FlexIO generates interrupts they could be on the A55 core(s) or the m33 core. I could not find where to decide which core gets the interrupt. Can I mix this, so individually decide on which core which pin generates which interrupt? Or is it separated by GPIO1/2/3/4 or FlexIO1/FlexIO2. Can someone point me to good docu or example about that. I tried the 5000 page manual for the CPU but with not much success

[Vitus]

Followup to question 1:

With some guesswork I got this for init:

#define SLAVE_FLEXIO_SPI_BASEADDR FLEXIO1
#define FLEXIO_SPI_PICKUP_PIN 6U
const flexio_gpio_config_t config =
{
  kFLEXIO_DigitalInput,
  0U,
  kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
};
FLEXIO_SetPinConfig(SLAVE_FLEXIO_SPI_BASEADDR, FLEXIO_SPI_PICKUP_PIN, &config); //sets up pin and interrupts

And for the interrupt I did

void FLEXIO1_IRQHandler(){
  // ??? FLEXIO_ClearPinsInterruptFlags(....); ???
  // do my stuff here
  SDK_ISR_EXIT_BARRIER;
}

Now, When I trigger a rising edge on the flexio pin, the interrupts comes now. But even if i do not touch the input pin anymore, the interrupt keeps coming. I assume there is a routinne to reset the interrupt flag somehow, but I could not find it. Has anyone a correct way to handle such an interrupt?  

[Vitus]

this solved the issue:

void FLEXIO1_IRQHandler()
{
  SLAVE_FLEXIO_SPI_BASEADDR->PINSTAT = (1u << FLEXIO_SPI_PICKUP_PIN);
  //do my stuff
  SDK_ISR_EXIT_BARRIER;
}

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

I found the following post that clears an interrupt generated by a Flex-IO, you could try to go with it.

https://community.nxp.com/t5/i-MX-Processors/i-MX93-Flexio-gpio-interrupt-issue/m-p/1840477

Regards