i.mx53 and ddr3

[didier1]

Hi

We are studying a board based on i.MX53.
We start from the QSB start-r design. We have a question, what is the topology used for the DDR3 memory?

T or fly-by?

thx

Didier

[JorgeRama_rezRi]

Hi Didier,

We use T topology on that specific board.

Best regards.

Jorge.

[didier1]

Hello
Thank you for your reply.
I asked the question because by reading the document MX53UG.pdf,

"If the data bus is two byte groups by memory, the topology is fly-by, as shown in Figure 2-10."

I had trouble understanding.

On the reference design I measured:
CLKxx: about 1130 mils

Data: about 600 mils

Address: about 1230 mils

I do not understand why the lengths of the addresses are longer than the clocks, because according to the same document TABLE 2.2, they should be between (clock and clock-200).

If routing is byte group, it is normal that the length of data is smaller than the clock.

Best regards

Didier

[JorgeRama_rezRi]

Hi Didier,

Sorry about the delay. I'm checking the MX53 QSB design and yes, the lengths of the DDR traces are not exactly as we recommend. To be honest, I don't know how the constraints were set on that design, but what I can say is: The success or failure of a specific design with these characteristics depends on the DDR operating factors. The guidelines we recommend assure a correct functionality of the DDR no matter its frequency. If the guidelines are not observed, the system has more probability to fail, but it doesn't mean it will fail. I'd recommend you to follow the guidelines so your system is robust enough to handle any possible issue.

I apologize about the confusion with the QSB design, but the guidelines in the UG will help you with signal integrity and good functionality of your system.

Best regards.
Jorge.