I am having trouble using a TI SN65DSI83 DSI to LVDS bridge with an iMX RT 117F.
My code is based on the 'lvgl demo widgets' example but the code has been modified so that the SN65DSI83 is initialised and appropriate parameters for my display are used - 50MHz LVDS clock and 300MHz DSI clock.
The display 'works', but the display will occasionally fade to white after the design has been running for a long time, and there's a 5% chance of that happening on startup if the reset button is pressed repeatedly. Reading the error register (0xE5) in the TI chip suggests that the PLL is losing lock (value of 0x01).
I added some code to periodically check the value of this error register and reinitialise the SN65DSI83 if a non-zero value is returned. This results in the screen being reinitialised a few times a minute, so this error bit is being triggered frequently.
I read that the SN65DSI83 is quite sensitive to jitter, so I've tried to measure it. The measurement below is from the LVDS output.
From the DSI clock generated by the NXP chip:
I've tried three different crystals and oscillators for the 24MHz clock and none of them gave any improvement.
I tried using a 25MHz oscillator on the TI chip's REFCLK pin as an alternative to using the DSI clock, and the jitter is much improved and the problem seems to have gone away. The below screenshot is of the LVDS output jitter.
I don't understand why the jitter is higher when using the DSI clock. It seems that I might be able to forego having to add the REFCLK oscillator if I can reduce the jitter of the DSI clock, or maybe the jitter is a 'red herring' and something else is causing the issue when using the DSI clock? It would be good to learn what causes this problem and maybe avoid having to rework a number of boards to add the REFCLK oscillator.
The main 24MHz oscillator has some jitter but not as much as the LVDS output:
I have not done anything to enable spread spectrum (I think it is disabled by default) and PLL_528 is used as the clock source for MIPI DSI.
