i.MX93 EQOS RMII mode in U-Boot

[muhammedk97]

Hello,

We have a new design based on i.MX93. LAN8720 (RMII PHY) is connected to EQOS port. We configured kernel device tree and it works without any problem.

But, in U-Boot, even though I can see 50 MHz clock on the pin, same device tree configuration does not work. When we try to ping, it gives the error below.

"EQOS_DMA_MODE_SWR stuck FAILED"

When I check the eqos driver in U-Boot "dwc_eth_qos.c", it's written in the explanation that "NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and supports a single RGMII PHY. This configuration also has SW control over all clock and reset signals to the HW block." . Should I understand eqos supports only RGMII in U-Boot?

How can I connect RMII phy with Eqos in U-Boot? Could you advice?

Regards,

[PBoerner]

I have the same problem with U-Boot. I have an external PHY in RMII mode and it provides the 50 MHz REFCLK to the CPU (verified).

I used the same pinctrl configuration as shown above and  I have set

- ENET QOS control signals (GPR) to 9 (ENET QOS Mode = RMII and ENET QOS = enabled)

- ENET CLK direction selection (ENET_CLK_SEL)  to 0 (TX_CLK of ENET QOS is input)

Reading the description about EQOS_DMA_MODE_SWR in the i.MX93 manual it sounds like the clock from the PHY is not entering the CPU at the right area and therfore the DMA reset does not work. I increased the wait time but without any differences.

When I look in imx93.dtsi I see that for FEC there is also a clock named IMX93_CLK_ENET_REF_PHY, but not for EQOS. How the CPU decides to use the external clock? Only be activating RMII mode and setting TXCLK as input? Or is something else missing in the devicetree configuration like IMX93_CLK_ENET_REF_PHY?

[muhammedk97]

Hi again,

After some debugging, I realized that when I ignore the error ethernet works fine and I can use ping without problem.

	ret = wait_for_bit_le32(&eqos->dma_regs->mode,
				EQOS_DMA_MODE_SWR, false,
				eqos->config->swr_wait, false);
	if (ret) {
		pr_err("EQOS_DMA_MODE_SWR stuck");
		goto err_stop_resets;
	}

When I comment out the if statement, it works.

Could you advice anything?

[Bio_TICFSL]

Hello,

Have checked your dtb?

I was able to resolve the issue by changing the direction of the RMII ref clock. Using an external clock (generated by the PHY) and adding snps,rmii_refclk_ext fixed the problem (without changing the pin configuration).

Have you ever tried using the RMII interface when generating the ref clock from the MAC?

My pinctrl:

  pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
			MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x91
			MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x91
			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x91
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x12
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x12
			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x12
			MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x1f
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
			MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x12
		>;
	};

Regards

[muhammedk97]

Could you check my last replay in the topic?

[muhammedk97]

Hello,

Thanks for the answer. I am not able to use external clock because it needs a design change. But, I can see the clock without any problem. It's generated as 50MHz.

Here is the kernel device tree, works fine.

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos_rmii>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	assigned-clock-rates = <100000000>, <50000000>;

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
			reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			interrupt-parent = <&gpio4>;
			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;	
		};
	};
};

	pinctrl_eqos_rmii: eqosrmiigrp {
		fsl,pins = <
			MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK         0x4000057e
			MX93_PAD_ENET1_MDC__ENET_QOS_MDC				0x57e
			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO				0x57e
			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0				0x57e
			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1				0x57e
			MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER				0x57e
			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x57e
			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x57e
			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1				0x57e
			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0				0x57e
			MX93_PAD_ENET1_RD3__GPIO4_IO13 					0x31e
			MX93_PAD_ENET1_RD2__GPIO4_IO12					0x31e
		>;
	};

Here is the u-boot device tree, which gives error: "EQOS_DMA_MODE_SWR stuck FAILED"

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos_rmii>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";
	assigned-clock-rates = <100000000>, <50000000>;
	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
			reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			interrupt-parent = <&gpio4>;
			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;	
		};
	};
};
	pinctrl_eqos_rmii: eqosrmiigrp {
		fsl,pins = <
			MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 	0x4000057e
			MX93_PAD_ENET1_MDC__ENET_QOS_MDC							0x57e
			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO							0x57e
			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0						0x57e
			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1						0x57e
			MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER							0x57e
			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL				0x57e
			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL				0x57e
			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1						0x57e
			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0						0x57e
			MX93_PAD_ENET1_RD3__GPIO4_IO13 					0x31e
			MX93_PAD_ENET1_RD2__GPIO4_IO12					0x31e
		>;
	};

Btw, I get the values from i.mx93 Ethernet Configuration Manual.