i.MX8X atomicity of the DMA

[AFR89]

Hello,

With the I.MX8X, what is the maximum atomicity for memory accesses made by the DMA?

I mean the ability of the DMA to write data at address X at the same time as a code read the data at address X, resulting in the data to be either fully written before the core read it or not written at all (the core reading the old data value).

Thanks

Alexandre

[AFR89]

Hi Igor,

Sorry I forget to precise, I was talking about the DMA of the PCIe driver.

Is it the same principle?

Best regards

Alexandre

[igorpadykov]

Hi Alexandre

in such case approach is the same, arbitration priority for various modules is configured

in SCFW, sect.16.31.4.12 board_qos_config() Porting Guide (sc_fw_port.pdf) included

in SCFW Porting Kit​

Best regards
igor

[igorpadykov]

Hi Alexandre

in such case approach is the same, arbitration priority for various modules is configured

in SCFW, sect.16.31.4.12 board_qos_config() Porting Guide (sc_fw_port.pdf) included

in SCFW Porting Kit​

Best regards
igor

[AFR89]

Hi,

Finally I find a wait de get the pdf. But I don't see how the QoS will have an impact on the atomicity the DMA PCIe will write in memory. So can you tell me what the size in bit the DMA PCIe can write atomically?

Best regards

Alexandre

[igorpadykov]

there is no such thing as PCIe "maximum atomicity for memory accesses".

That means that if PCIe DMA master starts "memory accesses" it will be finished

without interruption from other master, provided that other master has lower QoS settings

that PCIe.

Best regards
igor

[AFR89]

Hi,

Maybe my question is not clear, so I will try to reformulate it with an example.

If I start a PCIe frame with a payload of 64 Bytes, the DMA will start to read the RAM, the DMA can not read in 1 instruction all the data, so I guess it will repeat n time a read of x bits until it read all the data. So my question is more how many bits the DMA read by instruction in the RAM.

You can see the link https://community.nxp.com/t5/i-MX-Processors/i-MX8QXP-atomicity/m-p/1211789 where they talk about the atomicity between 2 cores. I try to know the same information but for the DMA.

Best regards

Alexandre

[igorpadykov]

i.MX8QXP subsystems are connected through SSI described in

sect.1.2.1.2 DRAM Block (DB), Figure 19-1. HSIO High-level Block Diagram, SSI is 128bits for HSIO.

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Best regards
igor

[AFR89]

Hi,

So if the DMA write the 128bits and a core try to access the same area in RAM, the DMA write and the core read after or invert without perturbation?

I want to be sure that if DMA write a value (>128 or 64bits) and a core try to read it in same time, the core will read the previous value or the new value but not something half updated.

Best regards

Alexandre

[igorpadykov]

>So if the DMA write the 128bits and a core try to access the same area in RAM,

>the DMA write and the core read after or invert without perturbation?

DMA and core QoS settings should be set properly to avoid perturbation.

DMA should have higher priority.

Best regards
igor

[AFR89]

So it mean that when the DMA is accessing the memory, the RAM is block for the core?

[igorpadykov]

if PCIe DMA master starts "memory accesses" it will be finished

without interruption from other master, provided that other master has lower QoS settings.

Good example of using processor arbiters priorities can be found in sect.3.3 NIC priorities AN4947

https://www.nxp.com/docs/en/application-note/AN4947.pdf

Best regards
igor

[AFR89]

Hi Igor,

When I download the archive from the link you gave me, I don't have pdf file in it.

Can you give me a link to the pdf file directly? thanks

Best regards

Alexandre

[igorpadykov]

Hi Alexandre

this depends on preemption configuration described in sect.14.5.4.2 eDMA arbitration

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Best regards
igor