Hi,
With i.MX 8X, what is the maximum reachable atomicity for memory accesses made between two Cortex-A35 cores? ARM documentation seems to suggest 64 bits. However, I am a bit puzzuled about this because the A35 cluster external AXI4 bus is 128 bit wide, so I would have expected it would be possible to atomically read/write 128bits from DDR in a single transaction.
We use DDR memory for exchanged data. The exchanged data is currently cacheable (shareable), but could be configured non-cacheable if that would help atomicity concerns.
We want to avoid reservation instruction (Load/Store Exclusive) because it requires a retry loop which increases the worst case execution time of the services exchanging data.
When we talk about 128 bits atomicity, we mean the ability of the SW on a core to write a 128 bits data at the same time as another core reads that 128 bits, resulting in the data to be either fully written before the second core reads it or not written at all (the second core reading the old 128 bits data value).
Thanks,
Étienne
