i.MX8QXP Pinmux problem with SPDIF0_RX/TX

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i.MX8QXP Pinmux problem with SPDIF0_RX/TX

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1,966件の閲覧回数
mod42
Contributor III

Hi

We have a custom iMX8XQP board where we want to use the pads SPDIF0_RX / SPDIF0_TX as GPIOs (LSIO_GPIO0_IO10 / LSIO_GPIO0_IO11). I added the following entries to the pinctrl_hog

 

IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10       0x00000041
IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11       0x00000041

 

 
and test the GPIOs through sysfs. The gpios are exported correctly and I can use the files in sysfs but the corresponding pins are always low. I used this approach with a couple of other GPIOs and there it works as expected. Is there anything special about these two pads?

 

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igorpadykov
NXP Employee
NXP Employee

Hi Matthias

 

as these pads are dual voltage pads one can try to add GPIORHB setting, described

in sect.9.2.5.1.75 IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB (IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB)

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual
as in example :
https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8x-mek.dt...

 

Best regards
igor

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1,956件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi Matthias

 

as these pads are dual voltage pads one can try to add GPIORHB setting, described

in sect.9.2.5.1.75 IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB (IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB)

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual
as in example :
https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8x-mek.dt...

 

Best regards
igor

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mod42
Contributor III

Sorry for the late replay. Adding this

 

IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0

 

to the device tree node pinctrl_hoghoggrp did the trick even it is not clear to me what the settings are changing. Setting bits 0 and 2 from field READ_NASRC which is not documented.
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