i.MX8MP LVDS cannot control VSYNC/HSYNC polarity (active high/low).

[dengxing]

Our product needs to send LVDS signals to an FPGA, which requires HSYNC and VSYNC to be active high. However, on the i.MX8MP, I cannot control the polarity of VSYNC/HSYNC (active high/low).The VSYNC and HSYNC signals from the i.MX8MP are always active low by default, but the FPGA requires them to be active high.

I tried the following two methods:

1、Configure LCDIF2 and LDB registers directly using devmem2 at runtime.

1.1、Configure LCDIF2，bit0～bit1，the FPGA signal capture shows no changes in VSYNC/HSYNC.

       # devmem2 0x32e90000 w

        Read at address  0x32E90000 (0xffff8cba2000): 0x00000003

        # devmem2 0x32e90008 w 0X3

        # devmem2 0x32e90000 w

        Read at address  0x32E90000 (0xffff8cba2000): 0x00000000
1.2、Configure LDB registers，bit9～bit10，the FPGA signal capture shows no changes in VSYNC/HSYNC.

       # devmem2 0x32ec005c w

        Read at address  0x32EC005C (0xffffb8a8005c): 0x000006B5

        # devmem2 0x32ec005c w 0xb5

        # devmem2 0x32ec005c w

        Read at address  0x32EC005C (0xffffb8a8005c): 0x000000B5

2、Use  the default dts ，Imx8mp-evk-jdi-wuxga-lvds-panel.dts

2.1、The compatible match uses auo,p320hvn03, with a resolution of 1920x1080, which is consistent with our current setup.

--- a/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-jdi-wuxga-lvds-panel.dts
@@ -3,11 +3,11 @@ 
 / {
        lvds0_panel {
-               compatible = "jdi,tx26d202vm0bwa";
+               compatible = "auo,p320hvn03";
                backlight = <&lvds_backlight>;
                port {

2.2、Modified the default configuration of auo,p320hvn03 and tested two versions for changes in VSYNC/HSYNC.

version a：

static const struct display_timing auo_p320hvn03_timings = {
        .vfront_porch = { 8, 17, 150 },
        .vback_porch = { 8, 17, 150 },
        .vsync_len = { 4, 11, 100 },
+       .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 };

Use devmem2 to print the values of the relevant registers.

Read at address  0x32E90000 (0xffffb93f5000): 0x00000003

Read at address  0x32E90010 (0xffffaf491010): 0x80000000

Read at address  0x32E90014 (0xffffaaa4c014): 0x04380780

Read at address  0x32E90018 (0xffffa8d98018): 0x00320032

Read at address  0x32E9001C (0xffff8b55101c): 0x00110011

Read at address  0x32E90020 (0xffffa23dd020): 0x000B0028

Read at address  0x32E90024 (0xffffb7089024): 0x00010005

Read at address  0x32E90028 (0xffff82b0c028): 0x00000000

Read at address  0x32E90030 (0xffff91be3030): 0x00000001

Read at address  0x32E90034 (0xffffa6532034): 0x00000001

Read at address  0x32E90200 (0xffff915a4200): 0x04380780

Read at address  0x32E90208 (0xffff8113f208): 0x00A21E00

Read at address  0x32E9020C (0xffffa288c20c): 0x66100000

Read at address  0x32E90210 (0xffff9f8d1210): 0x00000000

Read at address  0x32E90214 (0xffff960eb214): 0x89000000

Read at address  0x32E9021C (0xffffa9f8c21c): 0x00000001

Read at address  0x32E90220 (0xffffa2a91220): 0x00000000

Read at address  0x32E90224 (0xffffb4861224): 0x00000000

Read at address  0x32E90228 (0xffff82981228): 0x00000000

Read at address  0x32E9022C (0xffffb2e5322c): 0x00000000

Read at address  0x32E90230 (0xffffb5133230): 0x00000000

Read at address  0x32E90234 (0xffffbb901234): 0x00000000

Read at address  0x32E90238 (0xffffbca44238): 0x00AB0155

Read at address  0x32EC005C (0xffffa79fb05c): 0x000006B5

version b：

static const struct display_timing auo_p320hvn03_timings = {
        .vfront_porch = { 8, 17, 150 },
        .vback_porch = { 8, 17, 150 },
        .vsync_len = { 4, 11, 100 },
+       .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 };

Use devmem2 to print the values of the relevant registers.

Read at address  0x32E90000 (0xffffb6d9f000): 0x00000000

Read at address  0x32E90024 (0xffffa1510024): 0x00010005

Read at address  0x32E90028 (0xffffb93da028): 0x00000000

Read at address  0x32E90030 (0xffffb7111030): 0x00000001

Read at address  0x32E90034 (0xffff853b0034): 0x00000001

Read at address  0x32E90200 (0xffffae6e1200): 0x04380780

Read at address  0x32E90208 (0xffffb7106208): 0x00A21E00

Read at address  0x32E9020C (0xffffa44b020c): 0x66100000

Read at address  0x32E90210 (0xffffaa241210): 0x00000000

Read at address  0x32E90214 (0xffffb16cf214): 0x89000000

Read at address  0x32E9021C (0xffffad7e321c): 0x00000001

Read at address  0x32E90220 (0xffffb4e2a220): 0x00000000

Read at address  0x32E90224 (0xffff84b80224): 0x00000000

Read at address  0x32E90228 (0xffff8bd83228): 0x00000000

Read at address  0x32E9022C (0xffff920d922c): 0x00000000

Read at address  0x32E90230 (0xffff99008230): 0x00000000

Read at address  0x32E90234 (0xffffb5c39234): 0x00000000

Read at address  0x32E90238 (0xffff98c52238): 0x00AB0155

Read at address  0x32EC005C (0xffffa9dbd05c): 0x000000B5

but the FPGA signal capture shows no changes in VSYNC/HSYNC


Can you provide some suggestions or assistance?

[Zhiming_Liu]

Hello,

Please use the DISPLAY_FLAGS_VSYNC_HIGH and DISPLAY_FLAGS_HSYNC_HIGH in timing flag.

In the lcdifv3 driver, the polarity invert function is closed.

static struct lcdifv3_soc_pdata imx8mp_lcdif1_pdata = {
	.hsync_invert = false,
	.vsync_invert = false,
	.de_invert    = false,
};

static struct lcdifv3_soc_pdata imx8mp_lcdif2_pdata = {
	.hsync_invert = false,
	.vsync_invert = false,
	.de_invert    = false,
};

Best Regards,
Zhiming

[dengxing · Accepted solution]

Hi, Zhiming_Liu

Thanks for your help.We solved this issue.

The problem was that we configured the imx8mp.dtsi to keep the logo display consistent.This config made the VSYNC and HSYNC polarity settings in the kernel not take effect.

--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -395,6 +395,8 @@

mediamix_pd: mediamix-pd {
compatible = "fsl,imx8m-pm-domain";
+ active-wakeup;
+ rpm-always-on;
#power-domain-cells = <0>;
domain-index = <13>;
domain-name = "mediamix";

Finally, I changed the polarity settings in both U-Boot and the kernel, and that fixed the problem.