i.MX8MM MIPI CSI: can't read RX_FIFO register from CPU

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i.MX8MM MIPI CSI: can't read RX_FIFO register from CPU

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vincentz63
Contributor IV

For debugging purpose, we are trying to read the CSI RXFIFO 'manually', from code placed in mx6c_capture.c. We know the DMA is no longer running and there is data in the RXFIFO as DDRY is set.

The problem is the calls to csi_read() at address CSI_RFIFO return the same two 32bit values (which are valid), and the DDRY flag is never reset, even though the camera is no longer sending any data. So we are not emptying the FIFO.

CSI_RFIFO = Address: 32E2_0000h base + 10h offset = 32E2_0010h.

So it looks as if CSI_RFIFO is cached, or somehow we cannot empty the FIFO from the CPU. None of which make sense, nor match the Ref Manual, page 3992.

Questions:

* Why can't we read CSI_RFIFO from CPU?

* How can we read the content of the RXFIFO from CPU?

* Is there an undocumented register to know what the FIFO level is?

We have placed the code to read in function mx6s_csi_irq_handler() at a point where we know the DMA is no longer reading from the FIFO.

static inline int csi_read(struct mx6s_csi_dev *csi, unsigned int offset)
{
   return __raw_readl(csi->regbase + offset);
}
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vincentz63
Contributor IV

Anyone there?

We are drawing a blank trying to empty the CSI RXFIFO using CPU from the csi_bridge driver. We know we are reading the correct address as the two 32-bit words we get are what we expect, but why does the FIFO not empty?

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @vincentz63 

 

Can you try below code to clear FIFO?

	/* Clear RX FIFO */
	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 & ~BIT_FCC, CSI_CSICR1);
	cr1 = csi_read(csi_dev, CSI_CSICR1);
	csi_write(csi_dev, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
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vincentz63
Contributor IV
Hi Qmiller,
Thanks but I do not want to clear the FIFO, I want to read what data remains in it when the DMA halts.
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vincentz63
Contributor IV

Hello,

Anyone out there from NXP or not? This register is documented like any other register and I can find nothing in the Ref Manual that would explain why we cannot read it or how to do so...

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @vincentz63 

Normally, we can dump CSI registers from Linux userspace.These registers are defined in CSI IP SPEC, not in Reference Manual.

The CSI_RFIFO will only input DMA Contronller, i think you can't read FIFO if you halt DMA.

 

Qmiller_0-1664439142770.png

 

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vincentz63
Contributor IV

Hi Qmiller,

Thanks for getting back. What is the document your refer to? I do not seem to have it, where is it?

Does it contain other registers that are not documented in the Ref Manual? Can you check if there is a RFIFO LEVEL register please?

Are you saying that only the DMA engine can read this register and that the CPU cannot?

Thanks

JP

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

What is the document your refer to? I do not seem to have it, where is it?

-->We can't send it to customer.

 

 RFIFO LEVEL register

-->OFFSET: 8h, BIT[6:4]

 

000 4 Double words
001 8 Double words
010 16 Double words
011 24 Double words
100 32 Double words
101 48 Double words
110 64 Double words
111 96 Double words

 

 

Are you saying that only the DMA engine can read this register and that the CPU cannot?

-->You must read FIFO via DMA engine.CPU can't read it directly if you halt DMA. There is no direct connection between CPU and this register.

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