i.MX8M processor pins pull-up /down configuration

[nirmalluhana]

Hello gusarambula,

Thanks for your response.

As I gone through the datashhet from the link in last reply there is pins going in PD with 90K at reset time. But after reset condition if i set bits to pull-up enabled then it is going in pull-up condition using 90K or 27K value resistors.

Is my understanding correct? or I have to provide external pull-up resistors?

Best regards,

Nirmal

[Yuri · Accepted solution]

Hello,

  There is internal 90K Ohm pull down resistor on the IOs to avoid excessive current through the resistive voltage

divider of input receiver and to avoid receiver devices overstress at 2.5/3.3V voltage range. 
There is no control bit for pull down enable/disable. The pull down is described as “always on 90k pd res”

   For the PUE bit field, it only controls the internal 27K Ohm pull up resistor enable/disable.  Customers can

use IOMUXC registers, such as for example IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 to define what pins have

internal 27K Ohm pull up resistor enabled.

Have a great day,
Yuri

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[nirmalluhana]

Thanks, Yuri Muhin,

Appreciate your support.

Regards,

Nirmal