i.MX8M lpddr4 stress test failed at 1600MHz

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i.MX8M lpddr4 stress test failed at 1600MHz

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ken1zhang
Contributor II

Hi there,

We are using 16Gb LPDDR4 (speed 3200, x16, 2 Channel, 2 CS) on our custom i.MX8M board.  If we were to set "Clock Cycle Freq" in the "MX8M_LPDDR4_register_programming_aid_EVK_preliminiary_v17 " excel sheet to 800MHz, stress test will pass.  However, Stress test failed if "Clock Cycle Freq" were set to 1600MHz.   Does anyone has similar problem?  

1600MHz stress test result:

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
Actual DDR Clock rate being tested:
- DRC controller0: 800MHz, -DDR0 PHY: 1600MHz
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
.Address of test1 failure: 0x0000000080740000
Data was: 0xFFFFC0000000FFFE
But pattern was: 0xFFFFFFFF00000001
Source is wrong, it is: 0xFFFF225500000001
Address of source failure:0x0000000040740000

*****************************************************************************************************

800Mhz stress test result:

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
Actual DDR Clock rate being tested:
- DRC controller0: 400MHz, -DDR0 PHY: 800MHz
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test

Success: DDR Stress test completed!!!

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2,094 Views
carlos_ramos
Contributor I

Hello Igor,

I work with Ken's team. It looks like we have a working configuration. The solution on our end was using the latest v19 ds file along with changing MR3 and ATxImpedance. We compared the differences between v18 and v19 and it seems that the key factor was enabling WDQSExt as mentioned in the revision history. Our boards now pass the stress test with thousands of iterations. Perhaps the rd2wr and wr2rd timings are more stable that way? We will keep updating if anything changes.

Best Regards,
Carlos

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ken1zhang
Contributor II

Hi Igor,

Thanks for the update.   We actually ran into this problem on our 2nd revision board.   The first revision was using Micron's LPDDR4 memory (MT53D1024M32D4) and it passed memory stress test.   We replaced Micron with Hynix (H9HCNNNCPUMLHR-NLE)and start seeing the problem.   Is there additional layout guide line for Hynix memory?

Ken

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igorpadykov
NXP Employee
NXP Employee

Hi Ken

if this memory produces more noise that may require more margin than Micron chip

when implementing suggestions given in i.MX8M Hardware Developer’s Guide.

For Hynix memory one can try to tweak drive strength described in

sect.3.7.1 DDR I/O output buffer impedance i.MX8MDQ Datasheet
https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQCEC.pdf

Drive strength settings (Write Driver Impedance ) can be found in sect.4.2 Run DDR
Calibration and generate DDR initial code document MX8M_DDR_Tool_User_Guide.docx
included in i.MX8M DDR Test package.
i.MX8MSCALE DDR Tool Release 

In lpddr4 drive strength can be set with MR3.

Best regards
igor

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ken1zhang
Contributor II

Thank you, Igor for point us to the right direction.    I adjusted the value of MR3 in the ds file(0x31~0x09), stress still fails.  However, stress test DID pass after I change the value of ATxImpedance from initial 40 to 30.  DDR tool user guide describe ATxImpedance as following: "Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20)".   It doesn't provide detail in regards to the signal quality when different values are being used.  Can you shed more light on this particular parameter?   Thanks.

Ken 

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igorpadykov
NXP Employee
NXP Employee

Hi Ken

signal quality with different driver impedance values can be examined

using ibis modelling or with osilloscope, in general this depends on board layout.

Best regards
igor

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ken1zhang
Contributor II

Hello Igor,

After adjusting ATxImpedance from default value 0x40 to 0x30, we see our modules with 2GB memory are passing stress test with thousands iteration.  However, when we stress test module with 4GB memory,   it would fail at random iteration.   just to be clear on the value of MR3, lower the value means higher drive strength, correct?   

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igorpadykov
NXP Employee
NXP Employee

one can check power supplies ripple, for 4GB it can increase,

driver characteristics can be found in lpddr4 datasheet, like below

pastedImage_1.jpg

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi Ken

reason may be board memory layout, one can recheck it using suggestions given in

i.MX8M Hardware Developer’s Guide
https://www.nxp.com/docs/en/user-guide/IMX8MDQLQHDG.pdf

Best regards
igor
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