Hello,
I have an imx8mnano development board. Our goal is to run a bare-metal code on one of the A53 cores. I found a startup script which uses SRC_GPRx registers for storing startup addresses for secondary cores and SRC_A53RCR1 register for resetting a secondary core to start the core from the desired address previously saved. The script looks like:
Write 0x900000 0x14000000 // bare metal code, starting at OCRAM address 0x900000
....
Write 0x30390008 0x1 // disable secondary cores
Write 0x3039007C 0x2 // core 1 start addr high byte (0x900000>>22 && 0xFFFF)
Write 0x30390080 0x100000 // core 1 start addr low byte (0x900000 && 0x3FFFFF)
Write 0x30390008 0x3 // enable core 1 and keep running core 0
A uboot bootloader is already running on our development board (only core 0 is enabled by default and bootloader is running on core 0). I used tftp transfer to copy the code onto the OCRAM. Afterwards, I write/modify the registers shown in the above script using uboot commands i.e. mm (modify) and md (read/verify).
However, the core is not starting up. The bootloader is runnig normally after modifying SRC_A53RCR1 (0x30390008) register and enabling core 1. An increase in SoC current consumption is observed once the secondary core is enabled. But the program, which is supposed to turn on an led (4 lines of code), does nothing.
I am using aarch64-none-elf-gcc toolchain for building the c program. I was wondering if someone could help me with:
1. Is this the correct way to boot/start a A53 secondary core on iMx8M Nano processor?
2. Do we need to reset a secondary core (eg by using SRC_A53RCR0) as well as enable it or just enabling a secondary core using SRC_A53RCR1 (0x30390008) register should work?
3. Is the address calculation for SRC_GPR3 and SRC_GPR4 correct? The address conversion I am using right now is based on the reference manual and imx-atf repo c code, however the reference script I found shifts right by 2 in addition to 22 bits right shift as done in the imx-atf repo.
Thanks in advance
-Waseem
