i.MX6UL SPI

[anandkhandelwal]

We want to drive multiple serial devices on single SPI of i.MX6UL. However for that we need to know the output capacitance of SPI clock, SPI MOSI and SPI MISO.

I went through reference manual and datasheet, but could not get capacitance value.

Can you confirm that how many SPI slave devices I can connect. Or how much is the output capacitance of SPI clock, SPI MOSI and SPI MISO.

[igorpadykov]

Hi anand

capacitance can be found in ibis file

IBIS Model (2)

i.MX 6UltraLite Applications Processor|NXP

It is recommended to perform ibis modelling

to know how many SPI slave devices one can connect.

Best regards

igor

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[anandkhandelwal]

I went through the IBIS model and found out SPI clock capacitances of all four SPI channels. These capacitances are as follows:

---- CSI_DATA00 mapped to ESPI1_SCLK

CSI_DATA20 mapped to ESPI2_SCLK

NAND_CE0_B mapped to ESPI3_SCLK

CSI_DATA04 mapped to ESPI4_SCLK

So from above captured pictures we conclude that SPI clock capacitance varies from approx. 0.38pF to 0.56pF.

The chip we want to drive has input capacitance of 5pF, as per signal integrity rule it violates the condition.(As input cap is more than output cap)

Kindly let us know your inputs on this.

à CSI_DATA20 mapped to ESPI2_SCLK

[anandkhandelwal]

I went through the IBIS model and found out SPI clock capacitances of all four SPI channels. These capacitances are as follows:

----à CSI_DATA00 mapped to ESPI1_SCLK

à CSI_DATA20 mapped to ESPI2_SCLK

à NAND_CE0_B mapped to ESPI3_SCLK

à CSI_DATA04 mapped to ESPI4_SCLK

So from above captured pictures we conclude that SPI clock capacitance varies from approx. 0.38pF to 0.56pF.

The chip we want to drive has input capacitance of 5pF, as per signal integrity rule it violates the condition.(As input cap is more than output cap)

Kindly let us know your inputs on this.

----à CSI_DATA00 mapped to ESPI1_SCLK

à CSI_DATA20 mapped to ESPI2_SCLK

à NAND_CE0_B mapped to ESPI3_SCLK

à CSI_DATA04 mapped to ESPI4_SCLK