i.MX6SoloX: How to override boot mode selected by fuse bits?

[tpennanen]

Hi,

I seem to be having some issues understanding how the i.MX6SoloX ROM loader can be instructed to override eFuse selected boot mode by software.

The SRC_SBMR1 register description in Reference Manual chapter 61.7.2 states that setting SRC_GPR10[28] bit and desired boot configuration in SRC_GPR9 register should allow software to override the fuse bits and boot from an alternate boot source.

I'm trying to use U-Boot "bmode" command to configure the alternate boot source, but for some reason the ROM loader still always boots using the U-Boot SPL located on the eMMC selected by the fuse bits. I have also verified after the boot via JTAG that the persistent bits in SRC_GPR9 and SRC_GPR10 registers are still set, and that the boot was executed via WDOG reset (if that makes any difference).

I have tried to change the boot mode for example to USB serial loader with "bmode usb" and some nonexistent boot device with commands "bmode esdhc2" (empty SD-card slot) and "bmode sata".

Boot mode pin configuration is BOOT_MODE[1:0] = 0b00 (Boot From Fuses), BT_FUSE_SEL = 1, and DIR_BT_DIS = 1.

eFuses have been configured to boot from 8-bit eMMC connected to USDHC3 port:

• BOOT_CFG1 = 0x62
• BOOT_CFG2 = 0x52
• BOOT_CFG3 = 0x00
• BOOT_CFG4 = 0x00

Any ideas how to get boot override working in the ROM loader?

Best Regards,

Tuomas

[Yuri]

@tpennanen 
Hello,

   NXP i.MX6SX reference design total system POR is used for reboot (via WDOG).
Look at U41 (STM6779YWB6F) of the reference design. This means software
reboot is not working.

    It is highly recommended to remove power (voltage source) for all components on
the board in the event of a processor reset. This avoids having to determine if a
component critical to rebooting the processor is in the necessary state to support
a reboot.

Regards,
Yuri.

[tpennanen]

Hi Yuri,

Thanks for your reply. I have noticed that the reference design does generate a POR reset externally when WDOG_B signal is asserted, but I am using our own design, which doesn't have that circuitry.

When I read the SRC registers via JTAG after the reset, I can verify that WDOG reset was the reset reason, and that SRC_GPR9 & SRC_GPR10 still contain the boot mode value written by the "bmode" command before reset.

Do you mean that the software reboot is not working specifically on the reference design (which is understandable due to the POR reset), or that it is not working on the CPU?

[Yuri]

@tpennanen 
Hello,

    As has been mentioned, it is highly recommended to remove power for all components
on the board in the event of a processor reset to avoid unpredictable states.
 
   In particular: If the CPU is running at a low frequency, the PMIC can set the
voltage lower to conserve power. If the CPU is reset by POR_B, the PMIC will
keep the low voltage, which may not be sufficient for the ARM to boot at 800 MHz.

Regards,
Yuri.