i.MX6SDL fractional-N synthesizer

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i.MX6SDL fractional-N synthesizer

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satoshishimoda
Senior Contributor I

Hi community,

I want to confirm about fractional-N synthesizer of i.MX6SDL CCM.

Please see my questions below.

[Q1]

Please see chapter 18.5.1.3.3 in IMX6SDLRM Rev.1.

I understand fractional-N synthesizer is used for RF application generally.

However, i.MX6 system PLL is not connected to RF module directly.

So I guess this fractional-N synthesizer is prepared for spectrum spread.

Is my understanding correct?

[Q2]

Please see chapter 18.5.1.3.4.

It says "It has a Fractional-N synthesizer" for Audio/Video PLL, also.

However, I cannot find a register for setting fractional-N synthesizer of Audio/Video PLL.

Is the discription misprint?

If there is a fractional-N synthesizer, could you let me know how to set it?

Best Regards,

Satoshi Shimoda

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Yuri
NXP Employee
NXP Employee

1.

  Section 18.5.1.3.3 (System PLL) states about spread spectrum PLL output clock, that
allows to decrease radiated emission of the i.MX6. this may be needed to pass EMI

qualification tests if needed.

 

2.
In section 18.5.1.3.4 (Audio / Video PLL) :

PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)

As an example - for Audio - section 18.7.8 “Analog Audio PLL control Register

(CCM_ANALOG_PLL_AUDIOn)” describes the DIV_SELECT bit field, mentioned

in the formula above. 

As for the NUM : section 18.7.9 “Numerator of Audio PLL Fractional Loop Divider Register

(CCM_ANALOG_PLL_AUDIO_NUM)”


DENOM : section 18.7.10 “Denominator of Audio PLL Fractional Loop Divider

Register (CCM_ANALOG_PLL_AUDIO_DENOM)”

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Yuri
NXP Employee
NXP Employee

1.

  Section 18.5.1.3.3 (System PLL) states about spread spectrum PLL output clock, that
allows to decrease radiated emission of the i.MX6. this may be needed to pass EMI

qualification tests if needed.

 

2.
In section 18.5.1.3.4 (Audio / Video PLL) :

PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)

As an example - for Audio - section 18.7.8 “Analog Audio PLL control Register

(CCM_ANALOG_PLL_AUDIOn)” describes the DIV_SELECT bit field, mentioned

in the formula above. 

As for the NUM : section 18.7.9 “Numerator of Audio PLL Fractional Loop Divider Register

(CCM_ANALOG_PLL_AUDIO_NUM)”


DENOM : section 18.7.10 “Denominator of Audio PLL Fractional Loop Divider

Register (CCM_ANALOG_PLL_AUDIO_DENOM)”

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satoshishimoda
Senior Contributor I

Dear Yuri,

Thank you for your reply.

By your reply, I understood what does the manual mean.

It was simpler than I guessed.

It is the PLL which can change the dividing (multiplying) ratio with fraction, isn't it?

Best Regards,

Satoshi Shimoda

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Yuri
NXP Employee
NXP Employee

Yes.

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