i.MX6SDL GPIO unexpected behavior.

[satoshishimoda]

Hi community,

Our partner met a problem when I use a GPIO function of i.MX6.

Value of GPIO_DRI was cleared when I switched GPIO_GDIR.

Initialization flow was the following procedure.

① set value of GPIO_DR

② set value of GPIO_GDIR

But I set a port to 1 (high) and set GPIO_GDIR to 1 (output) of after that, then GPIO_DR value switched to 0 and it output low (our partner want to high signal).

As long as I read datasheet, I think that the above behavior doesn't occur.

Do you know the reason why the above behavior occurs?

Also, if I set value of GPIO_GDIR before I set value of GPIO_DR(29.4.2.2 GPIO Write Mode in i.MX 6Solo/6DualLite Applications Processor Reference Manual Rev.1, 04/2013), I think that a pulse exists for a moment.

In this case, Do you know how to prevent the pulse?

Best Regards,

Satoshi Shimoda

[Yuri · Accepted solution]

  Please try to enable GPIO module clocks before GPIO initialization.

//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================

setmem /32    0x020c4068 =    0xffffffff   

setmem /32    0x020c406c =    0xffffffff   

setmem /32    0x020c4070 =    0xffffffff   

setmem /32    0x020c4074 =    0xffffffff   

setmem /32    0x020c4078 =    0xffffffff   

setmem /32    0x020c407c =    0xffffffff   

setmem /32    0x020c4080 =    0xffffffff   

setmem /32    0x020c4084 =    0xffffffff

Have a great day,
Yuri

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[satoshishimoda]

Hi Yuri,

> setmem /32    0x020c4084 =    0xffffffff

There is no register on 0x020c4084.

Was this typo? Should we set 0xffffffff to 0x020c4088 (CCM_CMEOR register) instead of 0x020c4084?

Best Regards,

Satoshi Shimoda

[Yuri]

Yes, "setmem /32    0x020c4084 =    0xffffffff"  should be removed.

Regards,

Yuri.