i.MX6 PLL jitter behaviour

[sugiyamatoshihi]

Hi,

1. Is there Jitter specification of PLL5 in i.MX 6DQ.

2. Do you have a experience with below behaviour? 

We also observed wired behavior of PLL5.

Jitter distribution is periodically changing about 6 to 8 minutes. Jitter deviation become wider about every 6 minute and  during about 30 seconds. Also deviation seems depend on PLL Frequency.

Best Regards,

Sugiyama

[Yuri]

Hello,

  Jitter or accuracy parameters of internal PLLs are not specified.

One can refer to Table 2-20 (24 MHz crystal tolerance guidelines)

of Hardware Development Guide for i.MX 6 , assuming stability

(thermal, voltage and other) of PLL output clock is fully defined by

external crystal / oscillator, and i.MX6 meets USB, PCIe, Ethernet

clock specs.

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf 

  The issue, You described may be concerned with improper i.MX6 environment.

Please verify recommendations of the Guide, linked above regarding supply voltages,

bulk capacitors ; note, minimum 85mohm external ESR is required for VDD_HIGH_CAP.

Please refer to EB814 for detailed.

http://www.nxp.com/assets/documents/data/en/engineering-bulletins/EB814.pdf 

Have a great day,
Yuri

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[sugiyamatoshihi]

Hi, Yuri,

Thank you for reply.

I 'm disapointed that there is no jitter spec. Don't you have any actual data of jitter?

I already asked customer to check VDD 2.5V. Do you have any idea to explain why jitter become worse about every 6 minutes?

Best Regards,

Sugiyama

[Yuri]

Hello,

  I think the problem concerns with noisy environment, say - power supply glitches.

Regards,

Yuri.

[sugiyamatoshihi]

Hi, Yuri,

We checked i.MX6DQ AI board. It appears the same behaviour, but jitter value change is smaller than  customer board.

Do you think i.MX6 AI board have glitches?

Best Regards,

Sugiyama 

[Yuri]

Please let me know details how the jitters were measured.

Regards,

Yuri.

[sugiyamatoshihi]

Hi, Yuri,

I interrupt uboot and set the registers value like below to get 33MHz lvds clock.

PLL5 registers

CCM_ANALOG_PLL_VIDEOn               0x020C80A0 80002026
CCM_ANALOG_PLL_VIDEO_NUM       0x020C80B0 00000001
CCM_ANALOG_PLL_VIDEO_DENOM  0x020C80C0 00000002 

Set mux to PLL5

CCM_ANALOG_MISC2n   0xFA0C8170 00676767
CCM_CHSCCDR     0xFA0C4034 0002a003
CCM_CS2CDR     0xFA0C402C 007200c1
CCM_CSCDR2     0xFA0C4038 00000804
CCM_CSCMR2     0xFA0C4020 02a12f06
CCGR3       0xFA0C4074 ffffffff

Then, we observed the waveform and jitter distribution pin LVDS0_TX0_P output on LVDS0_CLK_POS of SBRE AI board.

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Yuri,

Do you have any idea to explain why jitter iincrease every 6minute?

I have to write FTA.

Best Rergards,

Sugiyama

[Yuri]

Hello,

There is no PLL5 issue reported before.

Regards,

Yuri.

[Yuri]

Hello,

 I've sent You content on the mentioned discussion.

Regards,

Yuri.

[sugiyamatoshihi · Accepted solution]

Hi, Yuri,

Thank you for your support.

We found the root cause of the issue that customer use wrong PLL setting procedure.

It need appropriate procedure to change PLL NUM, DENOM registers.

Customer didn't follow the procedure that reference manual describe 

"Before changing the PLL setting, power it down. Power up the PLL after the change"

in below section.

18.5.1.5.3 PLL clock change

In order to modify or stop the clock output of a specific PLL, all the clocks generated

from the current PLL must be transitioned to the new PLL whose frequency is not being

modified.

For clocks which can't be stopped (core and bus clocks), this should be done via the

glitchless mux. Before changing the PLL setting, power it down. Power up the PLL after

the change. See Disabling / Enabling PLLs for more information

We tested to set DENOM, NUM and DIV before POWER DOWN bit  clear, the issue disappeared. 

Also we requested the customer to use lager DENOM value to make PLL stable.

Best Regards,

Sugiyama