i.MX6 Display Configuration 2 Register 0

[sugiyamatoshihi]

Hi, 

I have a question about Display Configuration 2 Register 0, SL_0.

When I use parallel LCD 800x480 pix and set SL_0 =0x320, however if it set 0x0, nothing change. Display can show the picture.

What is this register configured?

Best Regards,

Sugiyama

[igorpadykov]

Hi Sugiyama

what is full processor name and any reference to

"Display Configuration 2 Register 0, SL_0" in processor documentation

(reference manual, page number e.t.c.) ?

Best regards
igor
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[sugiyamatoshihi]

Hi, Igor,

Thank you for reply.

I'm sorry less information.

Device is i.MX 6DQ and reference manual is IMX6DQRM rev4, below register.

I use IPU1 and address is 0x265_80E8 with Parallel Display CLAA-WVGA with SABRESD.

I use a command  [setenv mmcargs 'setenv bootargs console=${console},${baudrate} ${smp} root=${mmcroot} video=mxcfb0:dev=lcd,CLAA-WVGA,if=RGB565'] at uboot , then boot up Linux. 

Then the resister value is 0x320=800pixel, but  I changed it, nothing happen.

What is configured by this register?

Best Regards,

Sugiyama

[igorpadykov]

Hi Sugiyama

this register is used for smart lcds (with asynchronous interface) which are

not supported by i.MX6Q IPU.

Best regards
igor

[sugiyamatoshihi]

Hi, Igor,

Thank you for answer.

How we can sort out which registers are for asynchronous.?

I cannot distinguish them.

Best regards,

Sugiyama

[igorpadykov]

Hi Sugiyama

one can follow i.MX6Q IPU software described in Chapter 6 Image Processing

Unit (IPU) Drivers attached Linux Manual. Also by description, as below,

some register descriptions are used only for asynchronous lcds (serial type lcd is used only for smart lcds).

Best regards
igor