i.MX6 DDR3 calibration: How to calculate the value of DG_DL_ABS_OFFSET0 etc.

cancel
Showing results for 
Search instead for 
Did you mean: 

i.MX6 DDR3 calibration: How to calculate the value of DG_DL_ABS_OFFSET0 etc.

Jump to solution
554 Views
seiichinakano
Contributor II

Hi community,


I have a question about i.MX6 DDR3 caliblation (ddr_stress_tester_v2.40).

I'd like to calculate the actual delay of DG_DL_ABS_OFFSET0,WL_DL_ABS_OFFSET0,RD_DL_ABS_OFFSET0 and WR_DL_ABS_OFFSET0.

So,I used ddr_stress_tester_uboot_v2.40 with our custom mx6Q board.
And,I got the following result.

***result***
WL_DL_ABS_OFFSET0:0x23
DG_DL_ABS_OFFSET0:0x334
RD_DL_ABS_OFFSET0:0x5A
WR_DL_ABS_OFFSET0:0x34
************

While,
ARM core speed :1GHz      (1.0ns)
DDR_CLK frequency: 528MHz (1.894ns)

When I calculate the value of DG_DL_ABS_OFFSET0 etc. ,

which value should I choose out of 1GHz,528MHz or other frequency ?

According to "i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 2, 06/2014"(page 3977).

The following sentence exists.

"The delay of the delay-line would be (DG_DL_ABS_OFFSET0 / 256)* MMDC_CH0 AXI clock (fast clock)."

What is the value of  "MMDC_CH0 AXI clock(fast clock) " ?

I think it is 528MHz.

Is this correct or not ?

Likewise,what is the value of  "clock period" of "WL_DL_ABS_OFFSET0" ?

Best Regards,

Seiichi Nakano

Labels (2)
Tags (1)
0 Kudos
1 Solution
290 Views
Yuri
NXP TechSupport
NXP TechSupport

Hello,

1.
  The best-case and worst-case conditions, mentioned in the RM, relate to internal delays (gates), and are not frequency

dependent. «Moreover, when the operating clock is at the maximum allowed frequency, as appeared in the features list, then the delay-line is capable to issue a configurable delay of up to 1/2 clock cycle.»

2.
Yes, the CLK for "WL_DL_ABS_OFFSET0" is memory clock. Usually it is 528 MHz.

Regards,
Yuri.

View solution in original post

0 Kudos
5 Replies
290 Views
seiichinakano
Contributor II

Hello yuri

Thank you very much for your 2nd answer.

I understood at last.

Best Regards,

Seiichi Nakano

0 Kudos
291 Views
Yuri
NXP TechSupport
NXP TechSupport

Hello,

1.
  The best-case and worst-case conditions, mentioned in the RM, relate to internal delays (gates), and are not frequency

dependent. «Moreover, when the operating clock is at the maximum allowed frequency, as appeared in the features list, then the delay-line is capable to issue a configurable delay of up to 1/2 clock cycle.»

2.
Yes, the CLK for "WL_DL_ABS_OFFSET0" is memory clock. Usually it is 528 MHz.

Regards,
Yuri.

0 Kudos
290 Views
seiichinakano
Contributor II

Hello yuri

Thank you very much for your answer.

but,I have two additional questions.

((First question))
According to "i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 2, 06/2014"(page 3865).
The following sentence exists.

"Under best-case conditions, -40C, 1.21V - 1.6ns."

In this situation(Under best case),
what is the value of  "MMDC_CH0 AXI clock(fast clock) " ?

IF MMDC_CH0 AXI clock equal to 528MHz,
the maximum delay should be about 0.947ns( half cycle of 528MHz).

((Second question))
Is the CLK for "WL_DL_ABS_OFFSET0"  also 528MHz?

In MPWLDECTRL0 field descriptions, I couldn't find "MMDC_CH0 AXI clock(fast clock)" ,only "clock period" exists.

Best Regards,

Seiichi Nakano

0 Kudos
290 Views
b45499
NXP TechSupport
NXP TechSupport

Hi Seiichi Nakano ,

You can refer to i.MX6 DDR3 caliblation: How to calculate the value of DG_DL_ABS_OFFSET0 etc.​, our expert has given the reply to you.

Have a nice day.

Dan

0 Kudos
290 Views
seiichinakano
Contributor II

Thank you  DAN!

I will refer to the other thread.

Seiichi Nakano

0 Kudos