i.MX6 DDR3 Write leveling error

[sugiyamatoshihi]

Hi, 

I have a question about write leveling error on DDR3 in Hardware Write Leveling Calibration.

There return HW_WL_ERR and during HW write leveling sometimes. It seems calibration stop first DQS calibration and then it didn't go through fine tune.

Are there suspicious to stop fine tune calibration? Do you have a any experience like this?

Attached picture are OK case and NG case.  Left picture is OK case and right picture is NG case.

Best Regards,

Sugiyama

[Yuri]

Hello,

  According to section 44.11.6.1 (Hardware Write Leveling Calibration)

of i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015 :

" ...

8. MMDC repeates steps 5-7 till the write leveling delay is 1 cycle

9. MMDC checks the 8 bit prime DQ results for each DQS and finds the first transition from 0 to 1.

    If no transition is found then the MMDC indicates an error at MPWLGCR[HW_WL_ERR#].

..."

Have a great day,
Yuri

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[sugiyamatoshihi]

Hi, Yuri,

Thank you for the answer. 

However, according to waveform, there is one transition 0-1 in DQ at NG case, but error was set.

Do you think why this first transition couldn't found?

Should I check any other registers?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Yuri,

Do you have any comment on this?

However, according to waveform, there is one transition 0-1 in DQ at NG case, but error was set.

Do you think why this first transition couldn't found?

Should I check any other registers?

Best Regards,

Sugiyama

[Yuri]

Hello,

  Since HW_WL_ERR is set - there was no any 0->1 transition found. in the NG case.

Regards,

Yuri.

[sugiyamatoshihi]

Hi, Yuri,

I'm sorry I missed the register bit in MMDCx_MPWLGCR.

There is no error bit in WL_HW_ERRx, but WL_SW_RES2 was set.

It seems HW recognize as the 0->1 transistion when DQ is high at the first DQS.

However, I couldn't understand why there is no 0->1 tansition during fine tune.

Best Regards,

Sugiyama

[Yuri]

Hello,

  Again : 

  As for the case, when  DQS is high at the first DQS in Write Leveling Calibration : this is not a problem, since  just edge  of 0->1 transition event is important. DQS will be delayed for the next steps till “0” with following “1” will be detected.

   In Your situation - perhaps - some glitches  (on prime DQ) occur, interpreted as 0->1 edge by the MMDC. Also, please check DRAM datasheet regarding Write Leveling Calibration, it may be, that additional settings of DRAM Mode Registers should be performed.

Regards,

Yuri.

[sugiyamatoshihi]

Hi, Yuri,

There are further question.

When calibration tool run, Write leveling and DQS delay results are below.  DQS2 delay is 0/256 ,

and WL_DL_ABS_OFFSET2 (Byte2) in MMDC_MPWLDECTRL1 is 0x00 in the data. Then it seems it related to write leveling error.

Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0004000F
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00020000
Write DQS delay result:
Write DQS0 delay: 15/256 CK
Write DQS1 delay: 4/256 CK
Write DQS2 delay: 0/256 CK
Write DQS3 delay: 2/256 CK

What is supposed to cause by when this delays are 0?

Best Regards,

Sugiyama

[Yuri]

Hello,

  You may try the recommended after calibration values and if test is OK - why do not use them ?

Regards,

Yuri.